Favor; John Gregory

Patent Applications and Registrations

Patent applications and USPTO patent grants for Favor; John Gregory.The latest application filed is for "apparatus, system, and method for multi-level instruction scheduling in a microprocessor".

Company Profile

0.73.9

Favor; John Gregory - Santa Clara CA
Favor; John Gregory - San Francisco CA
Favor; John Gregory - Scotts Valley CA
Favor; John Gregory - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Flexible storage and optimized search for multiple page sizes in a translation lookaside buffer Grant 11,386,016 - Leming, III , et al. July 12, 2	2022-07-12
Apparatus, System, And Method For Multi-level Instruction Scheduling In A Microprocessor App 20220206845 - Mirkes; Sean Philip ; et al.	2022-06-30
Flexible Storage And Optimized Search For Multiple Page Sizes In A Translation Lookaside Buffer App 20220091997 - Leming, III; George Van Horn ; et al.	2022-03-24
Just-in-time Synonym Handling For A Virtually-tagged Cache App 20220004501 - Favor; John Gregory ; et al.	2022-01-06
Flexible Storage And Optimized Search For Multiple Page Sizes In A Translation Lookaside Buffer App 20210191877 - Leming, III; George Van Horn ; et al.	2021-06-24
Data management for cache memory Grant 10,372,615 - Svendsen , et al.	2019-08-06
Clock control based on voltage associated with a microprocessor Grant 10,348,281 - Oliver , et al. July 9, 2	2019-07-09
Data managment for cache memory Grant 9,798,672 - Svendsen , et al. October 24, 2	2017-10-24
Multi-level store merging in a cache and memory hierarchy Grant 9,280,479 - Kruckemyer , et al. March 8, 2	2016-03-08
Broadcast messaging and acknowledgment messaging for power management in a multiprocessor system Grant 9,213,643 - Kruckemyer , et al. December 15, 2	2015-12-15
Method and apparatus for performing table lookup Grant 9,058,284 - Ben-Meir , et al. June 16, 2	2015-06-16
Threshold controlled limited out of order load execution Grant 8,949,581 - Ashcraft , et al. February 3, 2	2015-02-03
Outstanding load miss buffer with shared entries Grant 8,850,121 - Ashcraft , et al. September 30, 2	2014-09-30
Broadcast Messaging And Acknowledgment Messaging For Power Management In A Multiprocessor System App 20140281275 - Kruckemyer; David Alan ; et al.	2014-09-18
Load store unit with load miss result buffer Grant 8,806,135 - Ashcraft , et al. August 12, 2	2014-08-12
Load miss result buffer with shared data lines Grant 8,793,435 - Ashcraft , et al. July 29, 2	2014-07-29
Virtual core management Grant 8,543,843 - Cheng , et al. September 24, 2	2013-09-24
Symbolic renaming optimization of a trace Grant 8,499,293 - Ashcraft , et al. July 30, 2	2013-07-30
Data cache rollbacks for failed speculative traces with memory operations Grant 8,370,609 - Favor , et al. February 5, 2	2013-02-05
Cache rollback acceleration via a bank based versioning cache ciruit Grant 8,370,576 - Favor , et al. February 5, 2	2013-02-05
Virtual core remapping based on temperature Grant 8,281,308 - Cheng , et al. October 2, 2	2012-10-02
Virtual core management Grant 8,225,315 - Cheng , et al. July 17, 2	2012-07-17
Trace based deallocation of entries in a versioning cache circuit Grant 8,051,247 - Favor , et al. November 1, 2	2011-11-01
Trace unit Grant 8,037,285 - Thaik , et al. October 11, 2	2011-10-11
System and method for ensuring coherency in trace execution Grant 8,032,710 - Ashcraft , et al. October 4, 2	2011-10-04
Memory ordering queue/versioning cache circuit Grant 8,024,522 - Favor , et al. September 20, 2	2011-09-20
Checking for a memory ordering violation after a speculative cache write Grant 8,019,944 - Favor , et al. September 13, 2	2011-09-13
Method and system for utilizing a common structure for trace verification and maintaining coherency in an instruction processing circuit Grant 8,015,359 - Favor , et al. September 6, 2	2011-09-06
Rolling back a speculative update of a non-modifiable cache line Grant 8,010,745 - Favor , et al. August 30, 2	2011-08-30
Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer Grant 7,987,342 - Thaik , et al. July 26, 2	2011-07-26
Concurrent vs. low power branch prediction Grant 7,966,479 - Thaik , et al. June 21, 2	2011-06-21
Trace unit with an op path from a decoder (bypass mode) and from a basic-block builder Grant 7,953,961 - Thaik , et al. May 31, 2	2011-05-31
Instruction cache, decoder circuit, basic block cache circuit and multi-block cache circuit Grant 7,953,933 - Thaik , et al. May 31, 2	2011-05-31
Trace unit with a trace builder Grant 7,949,854 - Thaik , et al. May 24, 2	2011-05-24
Method and system for promoting traces in an instruction processing circuit Grant 7,941,607 - Thaik , et al. May 10, 2	2011-05-10
Emit vector optimization of a trace Grant 7,937,564 - Ashcraft , et al. May 3, 2	2011-05-03
Trace based rollback of a speculatively updated cache Grant 7,877,630 - Favor , et al. January 25, 2	2011-01-25
Abort prioritization in a trace-based processor Grant 7,870,369 - Nelson , et al. January 11, 2	2011-01-11
Prediction of data values read from memory by a microprocessor using a dynamic confidence threshold Grant 7,856,548 - Nelson , et al. December 21, 2	2010-12-21
Flag optimization of a trace Grant 7,849,292 - Ashcraft , et al. December 7, 2	2010-12-07
Promoting and appending traces in an instruction processing circuit based upon a bias value Grant 7,814,298 - Thaik , et al. October 12, 2	2010-10-12
Virtual core management Grant 7,802,073 - Cheng , et al. September 21, 2	2010-09-21
Trace optimization via fusing operations of a target architecture operation set Grant 7,797,517 - Favor September 14, 2	2010-09-14
Virtual core management Grant 7,797,512 - Cheng , et al. September 14, 2	2010-09-14
Prediction of data values read from memory by a microprocessor using the storage destination of a load operation Grant 7,788,473 - Nelson , et al. August 31, 2	2010-08-31
Graceful degradation in a trace-based processor Grant 7,783,863 - Nelson , et al. August 24, 2	2010-08-24
Memory ordering queue tightly coupled with a versioning cache circuit Grant 7,779,307 - Favor , et al. August 17, 2	2010-08-17
Executing functions determined via a collection of operations from translated instructions Grant 7,681,019 - Favor March 16, 2	2010-03-16
Software hint to specify the preferred branch prediction to use for a branch instruction Grant 7,673,122 - Song , et al. March 2, 2	2010-03-02
Reduced-power memory with per-sector power/ground control and early address Grant 7,663,961 - Rowlands , et al. February 16, 2	2010-02-16
Flag management in processors enabled for speculative execution of micro-operation traces Grant 7,587,585 - Favor , et al. September 8, 2	2009-09-08
Flag management in processors enabled for speculative execution of micro-operation traces Grant 7,568,088 - Favor , et al. July 28, 2	2009-07-28
Flag management in processors enabled for speculative execution of micro-operation traces Grant 7,568,089 - Favor , et al. July 28, 2	2009-07-28
Prefetch hardware efficiency via prefetch hint instructions Grant 7,533,242 - Moll , et al. May 12, 2	2009-05-12
Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready Grant 7,493,471 - Favor , et al. February 17, 2	2009-02-17
Synchronizing master processor by stalling when tracking of coprocessor rename register resource usage count for sent instructions reaches credited apportioned number Grant 7,490,225 - Favor , et al. February 10, 2	2009-02-10
Dynamic resource allocation among master processors that require service from a coprocessor Grant 7,490,223 - Favor , et al. February 10, 2	2009-02-10
Reduced-power memory with per-sector ground control Grant 7,443,759 - Rowlands , et al. October 28, 2	2008-10-28
Adaptive computing ensemble microprocessor architecture Grant 7,389,403 - Alpert , et al. June 17, 2	2008-06-17
Microarchitecture for compact storage of embedded constants Grant 7,389,408 - Nelson , et al. June 17, 2	2008-06-17
Synchronized Register Renaming In A Multiprocessor App 20070198813 - Favor; John Gregory ; et al.	2007-08-23
Synchronized Register Renaming In A Multiprocessor App 20070198984 - Favor; John Gregory ; et al.	2007-08-23
Dynamic Resource Allocation App 20070198983 - Favor; John Gregory ; et al.	2007-08-23
Method and apparatus for debugging an integrated circuit Grant 6,499,123 - McFarland , et al. December 24, 2	2002-12-24
Method and apparatus for executing string instructions Grant 6,212,629 - McFarland , et al. April 3, 2	2001-04-03
Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions Grant 6,141,673 - Thayer , et al. October 31, 2	2000-10-31
Cache controller with table walk logic tightly coupled to second level access logic Grant 5,960,463 - Sharma , et al. September 28, 1	1999-09-28
Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions Grant 5,781,753 - McFarland , et al. July 14, 1	1998-07-14
Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions Grant 5,768,575 - McFarland , et al. June 16, 1	1998-06-16
Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Grant 5,682,492 - McFarland , et al. October 28, 1	1997-10-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.