| Patent | Date |
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Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries
Grant 11,397,686 - Favor , et al. July 26, 2 | 2022-07-26 |
Processor That Mitigates Side Channel Attacks By Refraining From Allocating An Entry In A Data Tlb For A Missing Load Address When The Load Address Misses Both In A Data Cache Memory And In The Data Tlb And The Load Address Specifies A Location Without A Valid Address Translation Or Without Permissi
App 20220108013 - Favor; John G. ; et al. | 2022-04-07 |
Processor That Mitigates Side Channel Attacks By Providing Random Load Data As A Result Of Execution Of A Load Operation That Does Not Have Permission To Access A Load Address
App 20220107784 - Favor; John G. ; et al. | 2022-04-07 |
Processor That Mitigates Side Channel Attacks By Prevents Cache Line Data Implicated By A Missing Load Address From Being Filled Into A Data Cache Memory When The Load Address Specifies A Location With No Valid Address Translation Or No Permission To Read From The Location
App 20220108012 - Favor; John G. ; et al. | 2022-04-07 |
Processor That Mitigates Side Channel Attacks By Preventing Cache Memory State From Being Affected By A Missing Load Operation By Inhibiting Or Canceling A Fill Request Of The Load Operation If An Older Load Generates A Need For An Architectural Exception
App 20220067156 - Favor; John G. ; et al. | 2022-03-03 |
Processor That Mitigates Side Channel Attacks By Expeditiously Initiating Flushing Of Instructions Dependent Upon A Load Instruction That Causes A Need For An Architectural Exception
App 20220067154 - Favor; John G. ; et al. | 2022-03-03 |
Virtually-tagged Data Cache Memory That Uses Translation Context To Make Entries Allocated During Execution Under One Translation Context Inaccessible During Execution Under Another Translation Context
App 20220067143 - Favor; John G. ; et al. | 2022-03-03 |
Processor That Mitigates Side Channel Attacks By Preventing All Dependent Instructions From Consuming Architectural Register Result Produced By Instruction That Causes A Need For An Architectural Exception
App 20220067155 - Favor; John G. ; et al. | 2022-03-03 |
Physically-tagged Data Cache Memory That Uses Translation Context To Reduce Likelihood That Entries Allocated During Execution Under One Translation Context Are Accessible During Execution Under Another Translation Context
App 20220067142 - Favor; John G. ; et al. | 2022-03-03 |
Processor That Prevents Speculative Execution Across Translation Context Change Boundaries To Mitigate Side Channel Attacks
App 20220027467 - Favor; John G. ; et al. | 2022-01-27 |
Microprocessor That Prevents Store-to-load Forwarding Between Different Translation Contexts
App 20220027459 - Favor; John G. | 2022-01-27 |
Microprocessor That Conditions Store-to-load Forwarding On Circumstances Associated With A Translation Context Update
App 20220027468 - Favor; John G. | 2022-01-27 |
Microprocessor Core With A Store Dependence Predictor Accessed Using A Translation Context
App 20220027460 - Favor; John G. | 2022-01-27 |
Digital processor for processing long and short pointers and converting each between a common format
Grant 8,656,139 - Meier , et al. February 18, 2 | 2014-02-18 |
Short Pointers
App 20120233414 - Meier; Stephan ; et al. | 2012-09-13 |
Method and apparatus for out-of-order processing of packets
Grant 7,852,846 - Favor , et al. December 14, 2 | 2010-12-14 |
Method and apparatus for out-of-order processing of packets using linked lists
Grant 7,808,999 - Chen , et al. October 5, 2 | 2010-10-05 |
Maintaining memory coherency with a trace cache
Grant 7,747,822 - Favor , et al. June 29, 2 | 2010-06-29 |
Method and apparatus for implementing a switching unit including a bypass path
Grant 7,512,129 - Favor , et al. March 31, 2 | 2009-03-31 |
Method and Apparatus for Out-of-Order Processing of Packets using Linked Lists
App 20080259928 - Chen; Edmund G. ; et al. | 2008-10-23 |
Method and apparatus for Out-of-Order Processing of Packets
App 20080259960 - Favor; John G. ; et al. | 2008-10-23 |
Method and apparatus for out-of-order processing of packets
Grant 7,349,398 - Favor , et al. March 25, 2 | 2008-03-25 |
Method and apparatus for out-of-order processing of packets using linked lists
Grant 7,349,399 - Chen , et al. March 25, 2 | 2008-03-25 |
Decoding suffix instruction specifying replacement destination for primary instruction
Grant 6,970,998 - Favor November 29, 2 | 2005-11-29 |
Cache retry request queue
Grant 6,732,236 - Favor May 4, 2 | 2004-05-04 |
Flexible implementation of a system management mode (SMM) in a processor
Grant 6,453,278 - Favor , et al. September 17, 2 | 2002-09-17 |
Branch prediction device with two levels of branch prediction cache
Grant 6,425,075 - Stiles , et al. July 23, 2 | 2002-07-23 |
Cache retry request queue
App 20020078302 - Favor, John G. | 2002-06-20 |
RISC86 instruction set
Grant 6,336,178 - Favor January 1, 2 | 2002-01-01 |
System and method for conditional moving an operand from a source register to destination register
Grant 6,298,438 - Thayer , et al. October 2, 2 | 2001-10-02 |
Prefetch instruction mechanism for processor
Grant 6,253,306 - Ben-Meir , et al. June 26, 2 | 2001-06-26 |
Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence
Grant 6,237,083 - Favor May 22, 2 | 2001-05-22 |
Unified multi-function operation scheduler for out-of-order execution in a superscaler processor
Grant 6,195,744 - Favor , et al. February 27, 2 | 2001-02-27 |
Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage
Grant 6,173,366 - Thayer , et al. January 9, 2 | 2001-01-09 |
Integration of multi-stage execution units with a scheduler for single-stage execution units
Grant 6,161,173 - Krishna , et al. December 12, 2 | 2000-12-12 |
Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values
Grant 6,154,831 - Thayer , et al. November 28, 2 | 2000-11-28 |
Method for reducing number of bits used in storage of instruction address pointer values
Grant 6,141,742 - Favor October 31, 2 | 2000-10-31 |
Flexible implementation of a system management mode (SMM) in a processor
Grant 6,093,213 - Favor , et al. July 25, 2 | 2000-07-25 |
Branch prediction device with two levels of branch prediction cache
Grant 6,067,616 - Stiles , et al. May 23, 2 | 2000-05-23 |
Scan chains for out-of-order load/store execution control
Grant 6,038,657 - Favor , et al. March 14, 2 | 2000-03-14 |
System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot
Grant 6,009,505 - Thayer , et al. December 28, 1 | 1999-12-28 |
RISC86 instruction set
Grant 5,926,642 - Favor July 20, 1 | 1999-07-20 |
Instruction decoder including two-way emulation code branching
Grant 5,920,713 - Favor July 6, 1 | 1999-07-06 |
Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device
Grant 5,920,515 - Shaik , et al. July 6, 1 | 1999-07-06 |
System and method for conditionally moving an operand from a source register to a destination register
Grant 5,909,572 - Thayer , et al. June 1, 1 | 1999-06-01 |
Unified multi-function operation scheduler for out-of-order execution in a superscalar processor
Grant 5,884,059 - Favor , et al. March 16, 1 | 1999-03-16 |
Processing system that rapidly indentifies first or second operations of selected types for execution
Grant 5,881,261 - Favor , et al. March 9, 1 | 1999-03-09 |
Self-modifying code handling system
Grant 5,826,073 - Ben-Meir , et al. October 20, 1 | 1998-10-20 |
Instruction buffer organization method and system
Grant 5,819,056 - Favor October 6, 1 | 1998-10-06 |
Instruction predecode and multiple instruction decode
Grant 5,809,273 - Favor , et al. September 15, 1 | 1998-09-15 |
Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles
Grant 5,801,975 - Thayer , et al. September 1, 1 | 1998-09-01 |
Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay
Grant 5,799,165 - Favor , et al. August 25, 1 | 1998-08-25 |
Instruction decoder including emulation using indirect specifiers
Grant 5,794,063 - Favor August 11, 1 | 1998-08-11 |
Out-of-order load/store execution control
Grant 5,754,812 - Favor , et al. May 19, 1 | 1998-05-19 |
Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence
Grant 5,748,932 - Van Dyke , et al. May 5, 1 | 1998-05-05 |
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
Grant 5,649,137 - Favor , et al. July 15, 1 | 1997-07-15 |
Two-level branch prediction cache
Grant 5,515,518 - Stiles , et al. May 7, 1 | 1996-05-07 |
Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
Grant 5,511,175 - Favor , et al. April 23, 1 | 1996-04-23 |
Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts
Grant 5,442,757 - McFarland , et al. * August 15, 1 | 1995-08-15 |
Two-level branch prediction cache
Grant 5,327,547 - Stiles , et al. * July 5, 1 | 1994-07-05 |
Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
Grant 5,230,068 - Van Dyke , et al. July 20, 1 | 1993-07-20 |
Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags
Grant 5,226,126 - McFarland , et al. July 6, 1 | 1993-07-06 |
Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
Grant 5,226,130 - Favor , et al. July 6, 1 | 1993-07-06 |
Two-level branch prediction cache
Grant 5,163,140 - Stiles , et al. November 10, 1 | 1992-11-10 |
Integrated single structure branch prediction cache
Grant 5,093,778 - Favor , et al. March 3, 1 | 1992-03-03 |
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