loadpatents
name:-0.30327916145325
name:-1.0114560127258
name:-0.017426013946533
Fastow; Richard Patent Filings

Fastow; Richard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fastow; Richard.The latest application filed is for "weak erase pulse".

Company Profile
14.56.31
  • Fastow; Richard - Cupertino CA
  • - Cupertino CA US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Weak Erase Pulse
App 20220293189 - Zhang; Chao ;   et al.
2022-09-15
Flash memory components and methods
Grant 11,322,508 - Parat , et al. May 3, 2
2022-05-03
Reducing Power Consumption In Nonvolatile Memory Due To Standby Leakage Current
App 20210096634 - FASTOW; Richard ;   et al.
2021-04-01
Memory arrays with bonded and shared logic circuitry
Grant 10,923,450 - Fastow , et al. February 16, 2
2021-02-16
Memory Arrays With Bonded And Shared Logic Circuitry
App 20200395328 - Fastow; Richard ;   et al.
2020-12-17
Program verify technique for non-volatile memory
Grant 10,847,234 - Zhao , et al. November 24, 2
2020-11-24
Program Verify Technique For Non-volatile Memory
App 20200342946 - ZHAO; Han ;   et al.
2020-10-29
Three-dimensional (3D) memory with shared control circuitry using wafer-to-wafer bonding
Grant 10,651,153 - Fastow , et al.
2020-05-12
Block by deck operations for NAND memory
Grant 10,325,665 - Fastow , et al.
2019-06-18
Flash Memory Components And Methods
App 20190043875 - PARAT; KRISHNA ;   et al.
2019-02-07
Three-dimensional (3d) Memory With Shared Control Circuitry Using Wafer-to-wafer Bonding
App 20190043836 - FASTOW; Richard ;   et al.
2019-02-07
Block By Deck Operations For Nand Memory
App 20190043591 - FASTOW; RICHARD ;   et al.
2019-02-07
Parallel bitline nonvolatile memory employing channel-based processing technology
Grant 9,431,109 - Nazarian , et al. August 30, 2
2016-08-30
CT-NOR differential bitline sensing architecture
Grant 9,362,293 - Nazarian , et al. June 7, 2
2016-06-07
Data pattern analysis
Grant 9,142,209 - Fastow , et al. September 22, 2
2015-09-22
Ct-nor Differential Bitline Sensing Architecture
App 20150179656 - Nazarian; Hagop ;   et al.
2015-06-25
Multi-pass Soft Programming
App 20150103601 - KATHAWALA; Gulzar A. ;   et al.
2015-04-16
Hidden Markov Model Processing Engine
App 20150106405 - BAPAT; Ojas ;   et al.
2015-04-16
Recognition of speech with different accents
Grant 9,009,049 - Liu , et al. April 14, 2
2015-04-14
Multi-pass soft programming
Grant 8,995,198 - Kathawala , et al. March 31, 2
2015-03-31
Arithmetic logic unit architecture
Grant 8,924,453 - Fastow , et al. December 30, 2
2014-12-30
Arithmetic logic unit architecture
Grant 08924453 -
2014-12-30
Apparatus and method for source side implantation after spacer formation to reduce short channel effects in metal oxide semiconductor field effect transistors
Grant 8,896,048 - Fastow , et al. November 25, 2
2014-11-25
Combining Of Results From Multiple Decoders
App 20140304205 - FASTOW; Richard ;   et al.
2014-10-09
Real-time data pattern analysis system and method of operation thereof
Grant 8,818,802 - Fastow , et al. August 26, 2
2014-08-26
DATA PATTERN ANALYSIS (as amended)
App 20140229178 - FASTOW; Richard ;   et al.
2014-08-14
High density NOR flash array architecture
Grant 8,754,463 - Fastow June 17, 2
2014-06-17
Parallel Bitline Nonvolatile Memory Employing Channel-based Processing Technology
App 20140146606 - Nazarian; Hagop ;   et al.
2014-05-29
Recognition of Speech With Different Accents
App 20140129218 - Liu; Chen ;   et al.
2014-05-08
Parallel bitline nonvolatile memory employing channel-based processing technology
Grant 8,681,558 - Nazarian , et al. March 25, 2
2014-03-25
Apparatus and method for a metal oxide semiconductor field effect transistor with source side punch-through protection implant
Grant 8,633,083 - Khan , et al. January 21, 2
2014-01-21
High read speed memory with gate isolation
Grant 8,520,437 - Fastow , et al. August 27, 2
2013-08-27
Acoustic Processing Unit
App 20130158996 - Fastow; Richard ;   et al.
2013-06-20
Arithmetic Logic Unit Architecture
App 20130159371 - Fastow; Richard ;   et al.
2013-06-20
High Read Speed Memory With Gate Isolation
App 20120327717 - Fastow; Richard ;   et al.
2012-12-27
High read speed memory with gate isolation
Grant 8,279,674 - Fastow , et al. October 2, 2
2012-10-02
Array type CAM cell for simplifying processes
Grant 8,237,210 - Wang , et al. August 7, 2
2012-08-07
High read speed electronic memory with serial array transistors
Grant 8,134,853 - Fastow , et al. March 13, 2
2012-03-13
High Read Speed Memory With Gate Isolation
App 20110317466 - Fastow; Richard ;   et al.
2011-12-29
High Density NOR Flash Array Architecture
App 20110156122 - Fastow; Richard
2011-06-30
High Read Speed Electronic Memory With Serial Array Transistors
App 20110149630 - Fastow; Richard ;   et al.
2011-06-23
Real-time Data Pattern Analysis System And Method Of Operation Thereof
App 20110082694 - FASTOW; Richard ;   et al.
2011-04-07
Parallel Bitline Nonvolatile Memory Employing Channel-based Processing Technology
App 20110080792 - Nazarian; Hagop ;   et al.
2011-04-07
High density NOR flash array architecture
Grant 7,910,976 - Fastow March 22, 2
2011-03-22
High density NOR flash array architecture
App 20090003060 - Fastow; Richard
2009-01-01
Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
Grant 7,301,193 - Fang , et al. November 27, 2
2007-11-27
Method for minimizing false detection of states in flash memory devices
Grant 7,283,398 - He , et al. October 16, 2
2007-10-16
Method, system, and circuit for performing a memory related operation
Grant 7,272,060 - Lu , et al. September 18, 2
2007-09-18
Memory device and method for erasing memory
Grant 7,187,591 - Fastow , et al. March 6, 2
2007-03-06
Memory Device And Method For Erasing Memory
App 20070002620 - Fastow; Richard ;   et al.
2007-01-04
Method and system for applying testing voltage signal
Grant 7,073,104 - Li , et al. July 4, 2
2006-07-04
Memory device with an alternating Vss interconnection
Grant 7,009,271 - Thurgate , et al. March 7, 2
2006-03-07
Minimization of FG-FG coupling in flash memory
Grant 6,996,004 - Fastow , et al. February 7, 2
2006-02-07
Memory array with memory cells having reduced short channel effects
Grant 6,963,106 - Fastow , et al. November 8, 2
2005-11-08
Reduced silicon gouging and common source line resistance in semiconductor devices
Grant 6,953,752 - He , et al. October 11, 2
2005-10-11
Structure and method for low Vss resistance and reduced dibl in a floating gate memory cell
App 20050164450 - Fang, Shenqing ;   et al.
2005-07-28
Memory cell array with staggered local inter-connect structure
Grant 6,911,704 - Randolph , et al. June 28, 2
2005-06-28
Memory cell array with staggered local inter-connect structure
App 20050077567 - Randolph, Mark W. ;   et al.
2005-04-14
Method and system for improving short channel effect on a floating gate device
Grant 6,878,589 - He , et al. April 12, 2
2005-04-12
Two-step source side implant for improving source resistance and short channel effect in deep sub-0.18.mu.m flash memory technology
Grant 6,852,594 - Wang , et al. February 8, 2
2005-02-08
Method of programming a memory cell
Grant 6,781,885 - Park , et al. August 24, 2
2004-08-24
Method for reducing short channel effects in memory cells and related structure
Grant 6,773,990 - Fastow , et al. August 10, 2
2004-08-10
Low column leakage flash memory array
Grant 6,768,683 - Fastow , et al. July 27, 2
2004-07-27
Method of programming memory cells
Grant 6,754,109 - Fastow , et al. June 22, 2
2004-06-22
Memory array with buried bit lines
Grant 6,737,703 - Fastow , et al. May 18, 2
2004-05-18
Virtual ground silicide bit line process for floating gate flash memory
Grant 6,716,698 - He , et al. April 6, 2
2004-04-06
Reduction of sector connecting line capacitance using staggered metal lines
Grant 6,700,201 - Fastow , et al. March 2, 2
2004-03-02
Method of matching core cell and reference cell source resistances
Grant 6,654,285 - Fastow , et al. November 25, 2
2003-11-25
Flash memory array architecture having staggered metal lines
Grant 6,646,914 - Haddad , et al. November 11, 2
2003-11-11
2Bit/cell architecture for floating gate flash memory product and associated method
Grant 6,570,211 - He , et al. May 27, 2
2003-05-27
Low Defect Density Process For Deep Sub-0.18mum Flash Memory Technologies
App 20030022440 - Wang, Zhigang ;   et al.
2003-01-30
Feedback method to optimize electric field during channel erase of flash memory devices
Grant 6,452,840 - Sunkavalli , et al. September 17, 2
2002-09-17
Low column leakage nor flash array-double cell implementation
Grant 6,449,188 - Fastow September 10, 2
2002-09-10
Lowered channel doping with source side boron implant for deep sub 0.18 micron flash memory cell
App 20020106852 - He, Yue-Song ;   et al.
2002-08-08
Low column leakage NOR flash array-single cell implementation
Grant 6,363,014 - Fastow March 26, 2
2002-03-26
Nitridization of the pre-ddi screen oxide
Grant 6,294,430 - Fastow , et al. September 25, 2
2001-09-25
Erase scheme to tighten the threshold voltage distribution of EEPROM flash memory cells
Grant 6,285,588 - Fastow September 4, 2
2001-09-04
Automatic program disturb with intelligent soft programming for flash cells
Grant 6,252,803 - Fastow , et al. June 26, 2
2001-06-26
APDE scheme for flash memory application
Grant 6,198,664 - Fastow March 6, 2
2001-03-06

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