| Patent | Date |
|---|
Three-dimensional memory device incorporating segmented array line memory array
Grant 8,659,028 - Scheuerlein , et al. February 25, 2 | 2014-02-25 |
Three-dimensional memory device incorporating segmented array line memory array
Grant 8,637,870 - Scheuerlein , et al. January 28, 2 | 2014-01-28 |
Three dimensional memory system with page of data across word lines
Grant 8,553,476 - Yan , et al. October 8, 2 | 2013-10-08 |
Memory array circuit incorporating multiple array block selection and related method
Grant 8,509,025 - Scheuerlein , et al. August 13, 2 | 2013-08-13 |
Capacitive discharge method for writing to non-volatile memory
Grant 8,310,892 - Scheuerlein , et al. November 13, 2 | 2012-11-13 |
Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same
Grant 8,279,704 - Scheuerlein , et al. October 2, 2 | 2012-10-02 |
Three Dimensional Memory System With Page Of Data Across Word Lines
App 20120224409 - Yan; Tianhong ; et al. | 2012-09-06 |
Non-volatile memory array architecture incorporating 1T-1R near 4F.sup.2 memory cell
Grant 8,233,309 - Fasoli July 31, 2 | 2012-07-31 |
Smart detection circuit for writing to non-volatile storage
Grant 8,111,539 - Fasoli , et al. February 7, 2 | 2012-02-07 |
Capacitive Discharge Method For Writing To Non-volatile Memory
App 20120008373 - Scheuerlein; Roy E. ; et al. | 2012-01-12 |
Memory Array Circuit Incorporating Multiple Array Block Selection And Related Method
App 20110299354 - Scheuerlein; Roy E. ; et al. | 2011-12-08 |
Capacitive discharge method for writing to non-volatile memory
Grant 8,059,447 - Scheuerlein , et al. November 15, 2 | 2011-11-15 |
Reversible-polarity decoder circuit and method
Grant 8,004,927 - Scheuerlein , et al. August 23, 2 | 2011-08-23 |
Non-volatile Memory Array Architecture Incorporating 1t-1r Near 4f2 Memory Cell
App 20110096588 - Fasoli; Luca G. | 2011-04-28 |
Decoder Circuitry Providing Forward And Reverse Modes Of Memory Array Operation And Method For Biasing Same
App 20110019495 - Scheuerlein; Roy E. ; et al. | 2011-01-27 |
Method for incorporating transistor snap-back protection in a level shifter circuit
Grant 7,696,804 - Thorp , et al. April 13, 2 | 2010-04-13 |
Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
Grant 7,697,366 - Fasoli , et al. April 13, 2 | 2010-04-13 |
Level shifter circuit incorporating transistor snap-back protection
Grant 7,696,805 - Thorp , et al. April 13, 2 | 2010-04-13 |
Capacitive Discharge Method For Writing To Non-volatile Memory
App 20090323393 - Scheuerlein; Roy E. ; et al. | 2009-12-31 |
Smart Detection Circuit For Writing To Non-volatile Storage
App 20090323392 - Fasoli; Luca G. ; et al. | 2009-12-31 |
Hierarchical bit line bias bus for block selectable memory array
Grant 7,633,828 - Scheuerlein , et al. December 15, 2 | 2009-12-15 |
Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
Grant 7,633,829 - Fasoli , et al. December 15, 2 | 2009-12-15 |
Method for using a hierarchical bit line bias bus for block selectable memory array
Grant 7,596,050 - Scheuerlein , et al. September 29, 2 | 2009-09-29 |
Memory device for protecting memory cells during programming
Grant 7,593,249 - Fasoli , et al. September 22, 2 | 2009-09-22 |
Method for protecting memory cells during programming
Grant 7,589,989 - Fasoli , et al. September 15, 2 | 2009-09-15 |
Method for using two data busses for memory array block selection
Grant 7,570,523 - Scheuerlein , et al. August 4, 2 | 2009-08-04 |
Method for using a spatially distributed amplifier circuit
Grant 7,558,140 - Fasoli , et al. July 7, 2 | 2009-07-07 |
Passive element memory array incorporating reversible polarity word line and bit line decoders
Grant 7,554,832 - Fasoli , et al. June 30, 2 | 2009-06-30 |
Spatially distributed amplifier circuit
Grant 7,554,406 - Fasoli , et al. June 30, 2 | 2009-06-30 |
Reversible-polarity Decoder Circuit And Method
App 20090161474 - Scheuerlein; Roy E. ; et al. | 2009-06-25 |
Method for reading a multi-level passive element memory cell array
Grant 7,542,338 - Scheuerlein , et al. June 2, 2 | 2009-06-02 |
Reversible polarity decoder circuit
Grant 7,542,370 - Yan , et al. June 2, 2 | 2009-06-02 |
Apparatus for reading a multi-level passive element memory cell array
Grant 7,542,337 - Scheuerlein , et al. June 2, 2 | 2009-06-02 |
Method for using a reversible polarity decoder circuit
Grant 7,525,869 - Yan , et al. April 28, 2 | 2009-04-28 |
Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block
Grant 7,508,714 - Fasoli , et al. March 24, 2 | 2009-03-24 |
Method for using dual data-dependent busses for coupling read/write circuits to a memory array
Grant 7,499,366 - Scheuerlein , et al. March 3, 2 | 2009-03-03 |
Dual data-dependent busses for coupling read/write circuits to a memory array
Grant 7,486,587 - Scheuerlein , et al. February 3, 2 | 2009-02-03 |
Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders
Grant 7,463,546 - Fasoli , et al. December 9, 2 | 2008-12-09 |
Memory array incorporating two data busses for memory array block selection
Grant 7,463,536 - Scheuerlein , et al. December 9, 2 | 2008-12-09 |
Memory Device for Protecting Memory Cells during Programming
App 20080247213 - Fasoli; Luca G. ; et al. | 2008-10-09 |
NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
Grant 7,433,233 - Chen , et al. October 7, 2 | 2008-10-07 |
Method For Using A Spatially Distributed Amplifier Circuit
App 20080239839 - Fasoli; Luca G. ; et al. | 2008-10-02 |
Level Shifter Circuit Incorporating Transistor Snap-back Protection
App 20080238523 - Thorp; Tyler J. ; et al. | 2008-10-02 |
Spatially Distributed Amplifier Circuit
App 20080238541 - Fasoli; Luca G. ; et al. | 2008-10-02 |
Method For Incorporating Transistor Snap-back Protection In A Level Shifter Circuit
App 20080238522 - Thorp; Tyler J. ; et al. | 2008-10-02 |
Method for controlling current during programming of memory cells
Grant 7,420,850 - Fasoli September 2, 2 | 2008-09-02 |
Memory device for controlling current during programming of memory cells
Grant 7,420,851 - Fasoli September 2, 2 | 2008-09-02 |
Integrated Circuit Memory Array Configuration Including Decoding Compatibility With Partial Implementation Of Multiple Memory Layers
App 20080192524 - Fasoli; Luca G. ; et al. | 2008-08-14 |
Reversible Polarity Decoder Circuit
App 20080159053 - Yan; Tianhong ; et al. | 2008-07-03 |
Method For Using A Reversible Polarity Decoder Circuit
App 20080159052 - Yan; Tianhong ; et al. | 2008-07-03 |
Memory device for protecting memory cells during programming
Grant 7,391,638 - Fasoli , et al. June 24, 2 | 2008-06-24 |
System architecture and method for three-dimensional memory
Grant 7,383,476 - Crowley , et al. June 3, 2 | 2008-06-03 |
Hierarchical Decoding Of Dense Memory Arrays Using Multiple Levels Of Multiple-headed Decoders
App 20080101149 - Fasoli; Luca G. ; et al. | 2008-05-01 |
Method For Protecting Memory Cells During Programming
App 20080094892 - Fasoli; Luca G. ; et al. | 2008-04-24 |
Method For Controlling Current During Programming Of Memory Cells
App 20080094915 - Fasoli; Luca G. | 2008-04-24 |
Memory Device For Controlling Current During Programming Of Memory Cells
App 20080094916 - Fasoli; Luca G. | 2008-04-24 |
Memory Device For Protecting Memory Cells During Programming
App 20080094913 - Fasoli; Luca G. ; et al. | 2008-04-24 |
Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
Grant 7,359,279 - Fasoli , et al. April 15, 2 | 2008-04-15 |
Method For Reading A Multi-level Passive Element Memory Cell Array
App 20080025089 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Method For Using Dual Data-dependent Busses For Coupling Read/write Circuits To A Memory Array
App 20080025133 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Apparatus For Reading A Multi-level Passive Element Memory Cell Array
App 20080025088 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Method For Using A Passive Element Memory Array Incorporating Reversible Polarity Word Line And Bit Line Decoders
App 20080025132 - Fasoli; Luca G. ; et al. | 2008-01-31 |
Passive Element Memory Array Incorporating Reversible Polarity Word Line And Bit Line Decoders
App 20080025066 - Fasoli; Luca G. ; et al. | 2008-01-31 |
Method For Using Two Data Busses For Memory Array Block Selection
App 20080025134 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Hierarchical Bit Line Bias Bus For Block Selectable Memory Array
App 20080025093 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Memory Array Incorporating Two Data Busses For Memory Array Block Selection
App 20080025085 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Dual Data-dependent Busses For Coupling Read/write Circuits To A Memory Array
App 20080025131 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Method For Using A Hierarchical Bit Line Bias Bus For Block Selectable Memory Array
App 20080025094 - Scheuerlein; Roy E. ; et al. | 2008-01-31 |
Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation
Grant 7,298,665 - So , et al. November 20, 2 | 2007-11-20 |
Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
Grant 7,286,439 - Fasoli , et al. October 23, 2 | 2007-10-23 |
Nand Memory Array Incorporating Capacitance Boosting Of Channel Regions In Unselected Memory Cells And Method For Operation Of Same
App 20070242511 - Chen; En-Hsing ; et al. | 2007-10-18 |
Memory Array Incorporating Memory Cells Arranged In Nand Strings
App 20070217263 - Fasoli; Luca G. ; et al. | 2007-09-20 |
Decoding circuit for non-binary groups of memory line drivers
Grant 7,272,052 - Scheuerlein , et al. September 18, 2 | 2007-09-18 |
NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
Grant 7,233,522 - Chen , et al. June 19, 2 | 2007-06-19 |
Memory array incorporating memory cells arranged in NAND strings
Grant 7,221,588 - Fasoli , et al. May 22, 2 | 2007-05-22 |
Apparatus and method for memory operations using address-dependent conditions
Grant 7,218,570 - So , et al. May 15, 2 | 2007-05-15 |
Programmable system device having a shared power supply voltage generator for FLASH and PLD modules
Grant 7,180,813 - Matarrese , et al. February 20, 2 | 2007-02-20 |
Integrated circuit including memory array incorporating multiple types of NAND string structures
Grant 7,177,191 - Fasoli , et al. February 13, 2 | 2007-02-13 |
System and method of controlling a three-dimensional memory
Grant 7,149,119 - Fasoli December 12, 2 | 2006-12-12 |
Method and apparatus for incorporating block redundancy in a memory array
Grant 7,142,471 - Fasoli , et al. November 28, 2 | 2006-11-28 |
Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
App 20060221752 - Fasoli; Luca G. ; et al. | 2006-10-05 |
Decoding circuit for non-binary groups of memory line drivers
App 20060221702 - Scheuerlein; Roy E. ; et al. | 2006-10-05 |
Method and apparatus for incorporating block redundancy in a memory array
App 20060221728 - Fasoli; Luca G. ; et al. | 2006-10-05 |
Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation
App 20060145193 - So; Kenneth K. ; et al. | 2006-07-06 |
Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders
App 20060146639 - Fasoli; Luca G. ; et al. | 2006-07-06 |
Integrated circuit including memory array incorporating multiple types of NAND string structures
App 20060146608 - Fasoli; Luca G. ; et al. | 2006-07-06 |
Apparatus and method for memory operations using address-dependent conditions
App 20060133125 - So; Kenneth K. ; et al. | 2006-06-22 |
Programmable system device having a shared power supply voltage generator for FLASH and PLD modules
App 20060126415 - Matarrese; Stella ; et al. | 2006-06-15 |
System and method of controlling a three-dimensional memory
App 20060083069 - Fasoli; Luca G. | 2006-04-20 |
NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
Grant 7,023,739 - Chen , et al. April 4, 2 | 2006-04-04 |
Method of programming a monolithic three-dimensional memory
App 20060067127 - Fasoli; Luca G. ; et al. | 2006-03-30 |
Multibank memory on a die
Grant 6,965,527 - Fasoli , et al. November 15, 2 | 2005-11-15 |
Nand memory array incorporating multiple series selection devices and method for operation of same
App 20050128807 - Chen, En-Hsing ; et al. | 2005-06-16 |
NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same
App 20050122780 - Chen, En-Hsing ; et al. | 2005-06-09 |
Memory array incorporating memory cells arranged in NAND strings
App 20050122779 - Fasoli, Luca G. ; et al. | 2005-06-09 |
System architecture and method for three-dimensional memory
App 20040250183 - Crowley, Matthew P. ; et al. | 2004-12-09 |
NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same
App 20040145024 - Chen, En-Hsing ; et al. | 2004-07-29 |
Multibank memory on a die
App 20040100827 - Fasoli, Luca G. ; et al. | 2004-05-27 |
| 