| Patent | Date |
|---|
Means of control for reconfigurable computers
Grant 9,081,901 - Lewins , et al. July 14, 2 | 2015-07-14 |
Digital circuits with adaptive resistance to single event upset
Grant 8,278,979 - Farwell October 2, 2 | 2012-10-02 |
Digital circuits with adaptive resistance to single event upset
Grant 8,040,157 - Farwell October 18, 2 | 2011-10-18 |
Digital Circuits With Adaptive Resistance To Single Event Upset
App 20110057700 - Farwell; William D. | 2011-03-10 |
Digital Circuits With Adaptive Resistance To Single Event Upset
App 20110057692 - Farwell; William D. | 2011-03-10 |
Digital circuits with adaptive resistance to single event upset
Grant 7,795,927 - Farwell September 14, 2 | 2010-09-14 |
Means of control for reconfigurable computers
App 20090113083 - Lewins; Lloyd J. ; et al. | 2009-04-30 |
Digital circuits with adaptive resistance to single event upset
App 20090045834 - Farwell; William D. | 2009-02-19 |
System and method for minimizing upsets in digital microcircuits via ambient radiation monitoring
Grant 6,948,080 - Farwell September 20, 2 | 2005-09-20 |
Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster
Grant 6,920,545 - Farwell , et al. July 19, 2 | 2005-07-19 |
Programmable bandwidth allocation between send and receive in a duplex communication path
Grant 6,775,248 - Farwell , et al. August 10, 2 | 2004-08-10 |
System and method for minimizing upsets in digital microcircuits
App 20040078660 - Farwell, William D. | 2004-04-22 |
Techniques for alignment of multiple asynchronous data sources
Grant 6,671,754 - Farwell December 30, 2 | 2003-12-30 |
Mixed technology microcircuits
Grant 6,667,519 - Farwell , et al. December 23, 2 | 2003-12-23 |
Reconfigurable processor architectures
App 20030135710 - Farwell, William D. ; et al. | 2003-07-17 |
Mixed technology microcircuits
App 20030015761 - Farwell, William D. ; et al. | 2003-01-23 |
Preheating device for electronic circuits
Grant 5,896,259 - Farwell , et al. April 20, 1 | 1999-04-20 |
Scan testing digital logic with differing frequencies of system clock and test clock
Grant 5,717,702 - Stokes , et al. February 10, 1 | 1998-02-10 |
Series connection of multiple digital devices to a single power source
Grant 5,703,790 - Farwell December 30, 1 | 1997-12-30 |
Method of applying boundary test patterns
Grant 5,606,565 - Edler , et al. February 25, 1 | 1997-02-25 |
Sample and hold flip-flop for CMOS logic
Grant 5,576,645 - Farwell November 19, 1 | 1996-11-19 |
Boundary test cell with self masking capability
Grant 5,528,610 - Edler , et al. June 18, 1 | 1996-06-18 |
High impedance technique for testing interconnections in digital systems
Grant 5,473,617 - Farwell December 5, 1 | 1995-12-05 |
Method for testing the electrical parameters of inputs and outputs of integrated circuits without direct physical contact
Grant 5,457,381 - Farwell October 10, 1 | 1995-10-10 |
Test flip-flop with an auxillary latch enabling two (2) bits of storage
Grant 5,329,167 - Farwell July 12, 1 | 1994-07-12 |
Method for self regulating CMOS digital microcircuit burn-in without ovens
Grant 5,233,161 - Farwell , et al. August 3, 1 | 1993-08-03 |
Conformal circuit for structural health monitoring and assessment
Grant 5,184,516 - Blazic , et al. February 9, 1 | 1993-02-09 |
Built-in test circuitry providing simple and accurate AC test of digital microcircuits with low bandwidth test equipment and probe stations
Grant 5,181,191 - Farwell January 19, 1 | 1993-01-19 |
Real time dynamic range compression for image enhancement
Grant 4,445,138 - Zwirn , et al. April 24, 1 | 1984-04-24 |
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