loadpatents
name:-0.014400005340576
name:-0.010179042816162
name:-0.0010318756103516
Farrow; Reginald Conway Patent Filings

Farrow; Reginald Conway

Patent Applications and Registrations

Patent applications and USPTO patent grants for Farrow; Reginald Conway.The latest application filed is for "smart shunt devices and methods".

Company Profile
0.9.9
  • Farrow; Reginald Conway - Somerset NJ
  • Farrow; Reginald Conway - East Brunswick NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Smart shunt devices and methods
Grant 9,861,524 - Thomas , et al. January 9, 2
2018-01-09
Smart Shunt Devices And Methods
App 20140309577 - Thomas; Gordon Albert ;   et al.
2014-10-16
Vibration powered impact recorder (VPIR)
Grant 8,571,835 - Farrow , et al. October 29, 2
2013-10-29
No clog shunt using a compact fluid drag path
Grant 8,088,091 - Thomas , et al. January 3, 2
2012-01-03
Nanotube Device and Method of Fabrication
App 20110240480 - Farrow; Reginald Conway ;   et al.
2011-10-06
Nanotube device and method of fabrication
Grant 7,964,143 - Farrow , et al. June 21, 2
2011-06-21
Vibration Powered Impact Recorder (vpir)
App 20110004444 - Farrow; Reginald Conway ;   et al.
2011-01-06
No clog shunt using a compact fluid drag path
App 20100228179 - Thomas; Gordon A. ;   et al.
2010-09-09
Method of Forming Nanotube Vertical Field Effect Transistor
App 20100207103 - Farrow; Reginald Conway ;   et al.
2010-08-19
Method of forming nanotube vertical field effect transistor
Grant 7,736,979 - Farrow , et al. June 15, 2
2010-06-15
Method of Forming Nanotube Vertical Field Effect Transistor
App 20080315302 - Farrow; Reginald Conway ;   et al.
2008-12-25
Nanotube Device and Method of Fabrication
App 20080317631 - Farrow; Reginald Conway ;   et al.
2008-12-25
Alignment mark fabrication process to limit accumulation of errors in level to level overlay
Grant 6,440,816 - Farrow , et al. August 27, 2
2002-08-27
Alignment Mark Fabrication Process To Limit Accumulation Of Errors In Level To Level Overlay
App 20020102811 - Farrow, Reginald Conway ;   et al.
2002-08-01
Manufacturing system error detection
Grant 5,906,902 - Farrow May 25, 1
1999-05-25
Lithographic process for device fabrication utilizing back-scattered electron beam signal intensity for alignment
Grant 5,824,441 - Farrow , et al. October 20, 1
1998-10-20

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