Farrow; Reginald C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Farrow; Reginald C..The latest application filed is for "analytical nanoscope on a chip for sub-optical resolution imaging".

Company Profile

1.9.8

Farrow; Reginald C. - Somerset NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Analytical nanoscope on a chip for sub-optical resolution imaging Grant 10,501,315 - Farrow , et al. Dec	2019-12-10
Analytical Nanoscope On A Chip For Sub-optical Resolution Imaging App 20170334717 - Farrow; Reginald C. ; et al.	2017-11-23
Nanoprobe and methods of use Grant 9,689,829 - Farrow , et al. June 27, 2	2017-06-27
Nanoprobe And Methods Of Use App 20150276649 - Farrow; Reginald C. ; et al.	2015-10-01
System and method for directed self-assembly technique for the creation of carbon nanotube sensors and bio-fuel cells on single plane Grant 8,546,027 - Farrow , et al. October 1, 2	2013-10-01
Nanotube device and method of fabrication Grant 8,257,566 - Farrow , et al. September 4, 2	2012-09-04
System and Method for Directed Self-Assembly Technique for the Creation of Carbon Nanotube Sensors and Bio-Fuel Cells on Single Plane App 20100279179 - Farrow; Reginald C. ; et al.	2010-11-04
Method and apparatus for manufacturing multiple circuit patterns using a multiple project mask Grant 7,581,203 - Farrow , et al. August 25, 2	2009-08-25
Nanotube Devices and Vertical Field Effect Transistors App 20090045061 - Farrow; Reginald C. ; et al.	2009-02-19
Multi-layered semiconductor structure Grant 6,977,128 - Boulin , et al. December 20, 2	2005-12-20
Method and apparatus for manufacturing multiple circuit patterns using a multiple project mask App 20040268272 - Farrow, Reginald C. ; et al.	2004-12-30
Multi-layered semiconductor structure App 20040094847 - Boulin, David M. ; et al.	2004-05-20
Method of forming an alignment feature in or on a multi-layered semiconductor structure Grant 6,706,609 - Boulin , et al. March 16, 2	2004-03-16
Method of forming an alignment feature in or on a multilayered semiconductor structure Grant 6,576,529 - Boulin , et al. June 10, 2	2003-06-10
Method of forming an alignment feature in or on a multi-layered semiconductor structure App 20020004283 - Boulin, David M. ; et al.	2002-01-10

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