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name:-0.0095288753509521
name:-0.00038814544677734
Farrell; James Arthur Patent Filings

Farrell; James Arthur

Patent Applications and Registrations

Patent applications and USPTO patent grants for Farrell; James Arthur.The latest application filed is for "method and circuits for early detection of a full queue".

Company Profile
0.7.5
  • Farrell; James Arthur - Harvard MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and circuits for early detection of a full queue
Grant 8,090,930 - Fischer , et al. January 3, 2
2012-01-03
Timing verifier for MOS devices and related method
Grant 6,877,142 - Nassif , et al. April 5, 2
2005-04-05
Method and circuits for early detection of a full queue
App 20050038979 - Fischer, Timothy Charles ;   et al.
2005-02-17
Apparatus for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
Grant 6,675,288 - Farrell , et al. January 6, 2
2004-01-06
Method and apparatus for performing timing verification of a circuit
Grant 6,658,506 - Nassif , et al. December 2, 2
2003-12-02
Timing verifier for MOS devices and related method
App 20030149951 - Nassif, Nevine ;   et al.
2003-08-07
Method and circuits for early detection of a full queue
App 20030120898 - Fischer, Timothy Charles ;   et al.
2003-06-26
Method and circuits for early detection of a full queue
Grant 6,542,987 - Fischer , et al. April 1, 2
2003-04-01
Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
App 20020156997 - Farrell, James Arthur ;   et al.
2002-10-24
Method for mapping instructions using a set of valid and invalid logical to physical register assignments indicated by bits of a valid vector together with a logical register list
Grant 6,405,304 - Farrell , et al. June 11, 2
2002-06-11
Method For Mapping Instructions Using A Set Of Valid And Invalid Logical To Physical Register Assignments Indicated By Bits Of A Valid Vector Together With A Logical Register List
App 20020069346 - FARRELL, JAMES ARTHUR ;   et al.
2002-06-06
Speculative issue of instructions under a load miss shadow
Grant 6,098,166 - Leibholz , et al. August 1, 2
2000-08-01

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