| Patent | Date |
|---|
Dual Redistribution Layer Structure
App 20220246472 - Farooq; Mukta G. ; et al. | 2022-08-04 |
Dual redistribution layer structure
Grant 11,315,831 - Farooq , et al. April 26, 2 | 2022-04-26 |
Heterogeneous integration structure for artificial intelligence computing
Grant 11,211,378 - Farooq , et al. December 28, 2 | 2021-12-28 |
SOI wafers with buried dielectric layers to prevent CU diffusion
Grant 10,923,427 - Stamper , et al. February 16, 2 | 2021-02-16 |
Dual Redistribution Layer Structure
App 20210028061 - Farooq; Mukta G. ; et al. | 2021-01-28 |
Heterogeneous Integration Structure For Artificial Intelligence Computing
App 20210020627 - Farooq; Mukta G. ; et al. | 2021-01-21 |
Electromigration monitor
Grant 10,794,948 - Chen , et al. October 6, 2 | 2020-10-06 |
Ionizing radiation blocking in IC chip to reduce soft errors
Grant 10,784,200 - Farooq , et al. Sept | 2020-09-22 |
Electromigration monitor
Grant 10,677,833 - Chen , et al. | 2020-06-09 |
Methods of forming integrated circuit structure for joining wafers and resulting structure
Grant 10,636,759 - Farooq , et al. | 2020-04-28 |
Methods Of Forming Integrated Circuit Structure For Joining Wafers And Resulting Structure
App 20200066667 - Farooq; Mukta G. ; et al. | 2020-02-27 |
Thru-silicon-via structures
Grant 10,388,567 - Chen , et al. A | 2019-08-20 |
Soi Wafers With Buried Dielectric Layers To Prevent Cu Diffusion
App 20190172789 - Stamper; Anthony K ; et al. | 2019-06-06 |
Forming multi-sized through-silicon-via (TSV) structures
Grant 10,296,698 - Farooq , et al. | 2019-05-21 |
Split probe pad structure and method
Grant 10,276,461 - Melville , et al. | 2019-04-30 |
SOI wafers with buried dielectric layers to prevent CU diffusion
Grant 10,242,947 - Stamper , et al. | 2019-03-26 |
Split Probe Pad Structure And Method
App 20190043769 - Melville; Ian D.W. ; et al. | 2019-02-07 |
Implant after through-silicon via (TSV) etch to getter mobile ions
Grant 10,170,337 - Collins , et al. J | 2019-01-01 |
Ic Structure Including Tsv Having Metal Resistant To High Temperatures And Method Of Forming Same
App 20180337089 - Farooq; Mukta G. ; et al. | 2018-11-22 |
Methods of forming integrated circuit structure for joining wafers and resulting structure
Grant 10,103,119 - Farooq , et al. October 16, 2 | 2018-10-16 |
Tiled-stress-alleviating pad structure
Grant 10,096,557 - Misra , et al. October 9, 2 | 2018-10-09 |
Insulating a via in a semiconductor substrate
Grant 10,079,175 - Farooq , et al. September 18, 2 | 2018-09-18 |
IC structure on two sides of substrate and method of forming
Grant 10,068,899 - Melville , et al. September 4, 2 | 2018-09-04 |
IC structure including TSV having metal resistant to high temperatures and method of forming same
Grant 10,049,979 - Farooq , et al. August 14, 2 | 2018-08-14 |
Methods Of Forming Integrated Circuit Structure For Joining Wafers And Resulting Structure
App 20180218991 - Farooq; Mukta G. ; et al. | 2018-08-02 |
Device layer transfer with a preserved handle wafer section
Grant 10,037,911 - Stamper , et al. July 31, 2 | 2018-07-31 |
Forming Multi-sized Through-silicon-via (tsv) Structures
App 20180165402 - Farooq; Mukta G. ; et al. | 2018-06-14 |
Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
Grant 9,966,310 - Farooq , et al. May 8, 2 | 2018-05-08 |
Integrated Circuit Structure Having Deep Trench Capacitor And Through-silicon Via And Method Of Forming Same
App 20180108566 - Farooq; Mukta G. ; et al. | 2018-04-19 |
Ic Structure Including Tsv Having Metal Resistant To High Temperatures And Method Of Forming Same
App 20180108607 - Farooq; Mukta G. ; et al. | 2018-04-19 |
Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
Grant 9,929,085 - Fitzsimmons , et al. March 27, 2 | 2018-03-27 |
Electromigration Monitor
App 20180074110 - Chen; Fen ; et al. | 2018-03-15 |
Electromigration Monitor
App 20180074111 - Chen; Fen ; et al. | 2018-03-15 |
Tiled-stress-alleviating Pad Structure
App 20180061777 - MISRA; Ekta ; et al. | 2018-03-01 |
Ic Structure On Two Sides Of Substrate And Method Of Forming
App 20180053743 - Melville; Ian D. W. ; et al. | 2018-02-22 |
Thru-silicon-via Structures
App 20180047626 - CHEN; Fen ; et al. | 2018-02-15 |
Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
Grant 9,892,970 - Farooq , et al. February 13, 2 | 2018-02-13 |
Electromigration monitor
Grant 9,891,261 - Chen , et al. February 13, 2 | 2018-02-13 |
Soi Wafers With Buried Dielectric Layers To Prevent Cu Diffusion
App 20180012845 - Stamper; Anthony K. ; et al. | 2018-01-11 |
Device Layer Transfer With A Preserved Handle Wafer Section
App 20180005873 - Stamper; Anthony K. ; et al. | 2018-01-04 |
Tiled-stress-alleviating Pad Structure
App 20170358541 - MISRA; Ekta ; et al. | 2017-12-14 |
Tiled-stress-alleviating pad structure
Grant 9,842,810 - Misra , et al. December 12, 2 | 2017-12-12 |
Integrated Circuit Structure Having Deep Trench Capacitor And Through-silicon Via And Method Of Forming Same
App 20170352618 - Fitzsimmons; John A. ; et al. | 2017-12-07 |
Integrated Circuit Structure Having Deep Trench Capacitor And Through-silicon Via And Method Of Forming Same
App 20170352592 - Farooq; Mukta G. ; et al. | 2017-12-07 |
Flip chip alignment mark exposing method enabling wafer level underfill
Grant 9,824,925 - Farooq , et al. November 21, 2 | 2017-11-21 |
Device layer transfer with a preserved handle wafer section
Grant 9,818,637 - Stamper , et al. November 14, 2 | 2017-11-14 |
Thru-silicon-via structures
Grant 9,812,359 - Chen , et al. November 7, 2 | 2017-11-07 |
SOI wafers with buried dielectric layers to prevent Cu diffusion
Grant 9,806,025 - Stamper , et al. October 31, 2 | 2017-10-31 |
Insulating A Via In A Semiconductor Substrate
App 20170256447 - FAROOQ; MUKTA G. ; et al. | 2017-09-07 |
Insulating a via in a semiconductor substrate
Grant 9,728,450 - Farooq , et al. August 8, 2 | 2017-08-08 |
Strain engineering devices using partial depth films in through-substrate vias
Grant 9,728,506 - Farooq , et al. August 8, 2 | 2017-08-08 |
Implant After Through-silicon Via (tsv) Etch To Getter Mobile Ions
App 20170200620 - Collins; Christopher ; et al. | 2017-07-13 |
Device Layer Transfer With A Preserved Handle Wafer Section
App 20170186643 - Stamper; Anthony K. ; et al. | 2017-06-29 |
Soi Wafers With Buried Dielectric Layers To Prevent Cu Diffusion
App 20170186693 - Stamper; Anthony K. ; et al. | 2017-06-29 |
Strain Engineering Devices Using Partial Depth Films In Through-substrate Vias
App 20170162508 - Farooq; Mukta G. ; et al. | 2017-06-08 |
Protected through semiconductor via (TSV)
Grant 9,673,095 - Farooq , et al. June 6, 2 | 2017-06-06 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 9,673,176 - Cheng , et al. June 6, 2 | 2017-06-06 |
Wafer to wafer alignment
Grant 9,671,215 - Farooq , et al. June 6, 2 | 2017-06-06 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 9,666,563 - Cheng , et al. May 30, 2 | 2017-05-30 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 9,653,432 - Cheng , et al. May 16, 2 | 2017-05-16 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 9,653,431 - Cheng , et al. May 16, 2 | 2017-05-16 |
Visualization of alignment marks on a chip covered by a pre-applied underfill
Grant 9,633,925 - Sakuma , et al. April 25, 2 | 2017-04-25 |
Strain detection structures for bonded wafers and chips
Grant 9,553,054 - Farooq , et al. January 24, 2 | 2017-01-24 |
Integrated circuit (IC) chips with through silicon vias (TSV) and method of forming the IC
Grant 9,536,784 - Farooq , et al. January 3, 2 | 2017-01-03 |
Programmable electrical fuse in keep out zone
Grant 9,536,829 - Farooq , et al. January 3, 2 | 2017-01-03 |
Insulating A Via In A Semiconductor Substrate
App 20160379818 - COLLINS; CHRISTOPHER ; et al. | 2016-12-29 |
Integrated Circuit (ic) Chips With Through Silicon Vias (tsv) And Method Of Forming The Ic
App 20160379883 - Farooq; Mukta G. ; et al. | 2016-12-29 |
Insulating A Via In A Semiconductor Substrate
App 20160379876 - FAROOQ; MUKTA G. ; et al. | 2016-12-29 |
Flip Chip Alignment Mark Exposing Method Enabling Wafer Level Underfill
App 20160365281 - Farooq; Mukta G. ; et al. | 2016-12-15 |
Thru-silicon-via Structures
App 20160358821 - CHEN; Fen ; et al. | 2016-12-08 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 9,515,051 - Cheng , et al. December 6, 2 | 2016-12-06 |
Three dimensional organic or glass interposer
Grant 9,490,197 - Farooq , et al. November 8, 2 | 2016-11-08 |
Electronic Package That Includes A Plurality Of Integrated Circuit Devices Bonded In A Three-dimensional Stack Arrangement
App 20160300814 - FAROOQ; MUKTA G. ; et al. | 2016-10-13 |
Protected Through Semiconductor Via (tsv)
App 20160293487 - Farooq; Mukta G. ; et al. | 2016-10-06 |
Electronic package that includes a plurality of integrated circuit devices bonded in a three-dimensional stack arrangement
Grant 9,461,017 - Farooq , et al. October 4, 2 | 2016-10-04 |
Three dimensional integrated circuit integration using dielectric bonding first and through via formation last
Grant 9,406,561 - Farooq , et al. August 2, 2 | 2016-08-02 |
Structures and methods for monitoring dielectric reliability with through-silicon vias
Grant 9,404,953 - Chen , et al. August 2, 2 | 2016-08-02 |
Protected through semiconductor via (TSV)
Grant 9,401,323 - Farooq , et al. July 26, 2 | 2016-07-26 |
Handler wafer removal by use of sacrificial inert layer
Grant 9,401,303 - Cheng , et al. July 26, 2 | 2016-07-26 |
Wafer To Wafer Alignment
App 20160178344 - Farooq; Mukta G. ; et al. | 2016-06-23 |
Non-contiguous Dummy Structure Surrounding Through-substrate Via Near Integrated Circuit Wires
App 20160148863 - Chen; Fen ; et al. | 2016-05-26 |
Three Dimensional Organic Or Glass Interposer
App 20160141237 - FAROOQ; Mukta G. ; et al. | 2016-05-19 |
Method and structure of die stacking using pre-applied underfill
Grant 9,330,946 - Farooq , et al. May 3, 2 | 2016-05-03 |
Strain Detection Structures For Bonded Wafers And Chips
App 20160118348 - FAROOQ; Mukta G. ; et al. | 2016-04-28 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20160086915 - Cheng; Tien-Jen ; et al. | 2016-03-24 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20160086914 - Cheng; Tien-Jen ; et al. | 2016-03-24 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20160086925 - Cheng; Tien-Jen ; et al. | 2016-03-24 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20160086916 - Cheng; Tien-Jen ; et al. | 2016-03-24 |
Programmable Electrical Fuse In Keep Out Zone
App 20160079166 - Farooq; Mukta G. ; et al. | 2016-03-17 |
3-D integration using multi stage vias
Grant 9,263,324 - Farooq , et al. February 16, 2 | 2016-02-16 |
Forming BEOL line fuse structure
Grant 9,263,386 - Farooq , et al. February 16, 2 | 2016-02-16 |
In-situ thermoelectric cooling
Grant 9,257,361 - Farooq , et al. February 9, 2 | 2016-02-09 |
Bottom-up plating of through-substrate vias
Grant 9,257,336 - Farooq , et al. February 9, 2 | 2016-02-09 |
Handler Wafer Removal By Use Of Sacrificial Inert Layer
App 20160035616 - Cheng; Kangguo ; et al. | 2016-02-04 |
Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
Grant 9,252,133 - Collins , et al. February 2, 2 | 2016-02-02 |
Electromigration Monitor
App 20150380326 - Chen; Fen ; et al. | 2015-12-31 |
3D chip stack having encapsulated chip-in-chip
Grant 9,219,023 - Farooq , et al. December 22, 2 | 2015-12-22 |
Bonded structure employing metal semiconductor alloy bonding
Grant 9,214,388 - Farooq , et al. December 15, 2 | 2015-12-15 |
Via structure for three-dimensional circuit integration
Grant 9,214,435 - Farooq , et al. December 15, 2 | 2015-12-15 |
Bonded structure with enhanced adhesion strength
Grant 9,159,674 - Farooq , et al. October 13, 2 | 2015-10-13 |
Facilitating Chip Dicing For Metal-metal Bonding And Hybrid Wafer Bonding
App 20150255417 - Farooq; Mukta G. ; et al. | 2015-09-10 |
Wafer to wafer alignment by LED/LSD devices
Grant 9,105,517 - Farooq , et al. August 11, 2 | 2015-08-11 |
Semiconductor chip with a dual damascene wire and through-substrate via (TSV) structure
Grant 9,093,503 - Chen , et al. July 28, 2 | 2015-07-28 |
Semiconductor Chip With A Dual Damascene Wire And Through-substrate Via (tsv) Structure
App 20150194345 - Chen; Fen ; et al. | 2015-07-09 |
Structure and method for making crack stop for 3D integrated circuits
Grant 9,059,167 - Farooq , et al. June 16, 2 | 2015-06-16 |
Sidewalls of electroplated copper interconnects
Grant 9,060,457 - Farooq , et al. June 16, 2 | 2015-06-16 |
Forming BEOL line fuse structure
Grant 9,059,175 - Farooq , et al. June 16, 2 | 2015-06-16 |
Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
Grant 9,059,333 - Farooq , et al. June 16, 2 | 2015-06-16 |
Sidewalls of electroplated copper interconnects
Grant 9,055,703 - Farooq , et al. June 9, 2 | 2015-06-09 |
Facilitating Chip Dicing For Metal-metal Bonding And Hybrid Wafer Bonding
App 20150155263 - Farooq; Mukta G. ; et al. | 2015-06-04 |
Phase change memory management
Grant 9,047,938 - Farooq , et al. June 2, 2 | 2015-06-02 |
Sidewalls of electroplated copper interconnects
Grant 9,040,407 - Farooq , et al. May 26, 2 | 2015-05-26 |
Enhanced capture pads for through semiconductor vias
Grant 9,040,418 - Farooq , et al. May 26, 2 | 2015-05-26 |
Forming semiconductor chip connections
Grant 9,035,465 - Cheng , et al. May 19, 2 | 2015-05-19 |
Structures and Methds for Monitoring Dielectric Reliability With Through-Silicon Vias
App 20150115982 - Chen; Fen ; et al. | 2015-04-30 |
Method And Structure Of Forming Backside Through Silicon Via Connections
App 20150097273 - Farooq; Mukta G. ; et al. | 2015-04-09 |
Through-silicon Via Structure And Method For Improving Beol Dielectric Performance
App 20150097274 - Collins; Christopher ; et al. | 2015-04-09 |
Ionizing radiation blocking in IC chip to reduce soft errors
Grant 8,999,764 - Farooq , et al. April 7, 2 | 2015-04-07 |
Through-silicon Via Structure And Method For Improving Beol Dielectric Performance
App 20150069608 - Collins; Christopher ; et al. | 2015-03-12 |
3d Chip Crackstop
App 20150069609 - Farooq; Mukta G. ; et al. | 2015-03-12 |
Wafer To Wafer Alignment By Led/lsd Devices
App 20150069421 - Farooq; Mukta G. ; et al. | 2015-03-12 |
In-situ Thermoelectric Cooling
App 20150059361 - Farooq; Mukta G. ; et al. | 2015-03-05 |
Method and structure of forming backside through silicon via connections
Grant 8,970,011 - Farooq , et al. March 3, 2 | 2015-03-03 |
Co-axial restraint for connectors within flip-chip packages
Grant 8,970,041 - Farooq , et al. March 3, 2 | 2015-03-03 |
Bottom-up Plating Of Through-substrate Vias
App 20150056804 - Farooq; Mukta G. ; et al. | 2015-02-26 |
Computer readable medium encoded with a program for fabricating 3D integrated circuit device using interface wafer as permanent carrier
Grant 8,962,448 - Farooq , et al. February 24, 2 | 2015-02-24 |
Bottom-up plating of through-substrate vias
Grant 8,956,973 - Farooq , et al. February 17, 2 | 2015-02-17 |
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
Grant 8,951,906 - Farooq , et al. February 10, 2 | 2015-02-10 |
Via Structure For Three-dimensional Circuit Integration
App 20150035169 - Farooq; Mukta G. ; et al. | 2015-02-05 |
Computer Readable Medium Encoded With A Program For Fabricating 3d Integrated Circuit Device Using Interface Wafer As Permanent Carrier
App 20150024548 - Farooq; Mukta G. ; et al. | 2015-01-22 |
In-situ thermoelectric cooling
Grant 8,933,562 - Kinser , et al. January 13, 2 | 2015-01-13 |
Forming Beol Line Fuse Structure
App 20150004781 - Farooq; Mukta G. ; et al. | 2015-01-01 |
Electrical Leakage Reduction In Stacked Integrated Circuits Having Through-silicon-via (tsv) Structures
App 20150004749 - Collins; Christopher N. ; et al. | 2015-01-01 |
Semiconductor device having a copper plug
Grant 8,922,019 - Farooq , et al. December 30, 2 | 2014-12-30 |
Semiconductor device having a copper plug
Grant 08922019 - | 2014-12-30 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20140374903 - Cheng; Tien-Jen ; et al. | 2014-12-25 |
Metal to metal bonding for stacked (3D) integrated circuits
Grant 8,916,448 - Cheng , et al. December 23, 2 | 2014-12-23 |
Wafer Alignment And Bonding Tool For 3d Integration
App 20140370624 - Farooq; Mukta G. ; et al. | 2014-12-18 |
Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
Grant 8,907,494 - Collins , et al. December 9, 2 | 2014-12-09 |
Structure And Method For Making Crack Stop For 3d Integrated Circuits
App 20140339703 - Farooq; Mukta G. ; et al. | 2014-11-20 |
Method Of Forming A Through-silicon Via Utilizing A Metal Contact Pad In A Back-end-of-line Wiring Level To Fill The Through-silicon Via
App 20140342552 - Farooq; Mukta G. ; et al. | 2014-11-20 |
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
Grant 8,889,542 - Farooq , et al. November 18, 2 | 2014-11-18 |
Forming Semiconductor Chip Connections
App 20140332929 - Cheng; Kangguo ; et al. | 2014-11-13 |
Fluorine depleted adhesion layer for metal interconnect structure
Grant 8,871,636 - Farooq , et al. October 28, 2 | 2014-10-28 |
Structure and method for making crack stop for 3D integrated circuits
Grant 8,859,390 - Farooq , et al. October 14, 2 | 2014-10-14 |
3-D integration using multi stage vias
Grant 8,853,857 - Farooq , et al. October 7, 2 | 2014-10-07 |
Simultaneously forming a through silicon via and a deep trench structure
Grant 8,841,200 - Cheng , et al. September 23, 2 | 2014-09-23 |
Bonded structure employing metal semiconductor alloy bonding
Grant 8,841,777 - Farooq , et al. September 23, 2 | 2014-09-23 |
Stacked Integrated Circuit
App 20140264756 - Collins; Christopher N. ; et al. | 2014-09-18 |
Leakage measurement of through silicon vias
Grant 8,835,194 - Bhoovaraghan , et al. September 16, 2 | 2014-09-16 |
Front Side Wafer Id Processing
App 20140256130 - Farooq; Mukta G. ; et al. | 2014-09-11 |
Front side wafer ID processing
Grant 8,822,141 - Farooq , et al. September 2, 2 | 2014-09-02 |
Bonded Structure With Enhanced Adhesion Strength
App 20140239458 - Farooq; Mukta G. ; et al. | 2014-08-28 |
Phase Change Memory Management
App 20140241048 - Farooq; Mukta G. ; et al. | 2014-08-28 |
Method Of Forming A Through-silicon Via Utilizing A Metal Contact Pad In A Back-end-of-line Wiring Level To Fill The Through-silicon Via
App 20140227870 - Farooq; Mukta G. ; et al. | 2014-08-14 |
Forming semiconductor chip connections
Grant 8,802,497 - Hsu , et al. August 12, 2 | 2014-08-12 |
Method of forming a through-silicon via utilizing a metal contact pad in a back-end-of-line wiring level to fill the through-silicon via
Grant 8,791,009 - Farooq , et al. July 29, 2 | 2014-07-29 |
Sidewalls of electroplated copper interconnects
Grant 8,791,005 - Farooq , et al. July 29, 2 | 2014-07-29 |
In-situ Thermoelectric Cooling
App 20140203433 - Kinser; Emily ; et al. | 2014-07-24 |
Metal To Metal Bonding For Stacked (3d) Integrated Circuits
App 20140191418 - Cheng; Tien-Jen ; et al. | 2014-07-10 |
Enhanced capture pads for through semiconductor vias
Grant 8,772,949 - Farooq , et al. July 8, 2 | 2014-07-08 |
Edge protection seal for bonded substrates
Grant 8,771,533 - Farooq , et al. July 8, 2 | 2014-07-08 |
Fluorine depleted adhesion layer for metal interconnect structure
Grant 8,765,597 - Farooq , et al. July 1, 2 | 2014-07-01 |
Bonded structure with enhanced adhesion strength
Grant 8,748,288 - Farooq , et al. June 10, 2 | 2014-06-10 |
Semiconductor device having a copper plug
Grant 8,749,059 - Farooq , et al. June 10, 2 | 2014-06-10 |
Semiconductor device having a copper plug
Grant 8,741,769 - Farooq , et al. June 3, 2 | 2014-06-03 |
3D integrated circuit device fabrication with precisely controllable substrate removal
Grant 8,738,167 - Farooq , et al. May 27, 2 | 2014-05-27 |
Enhanced Capture Pads For Through Semiconductor Vias
App 20140124946 - Farooq; Mukta G. ; et al. | 2014-05-08 |
Method And Structure Of Forming Backside Through Silicon Via Connections
App 20140124954 - Farooq; Mukta G. ; et al. | 2014-05-08 |
Enhanced Capture Pads For Through Semiconductor Vias
App 20140127904 - Farooq; Mukta G. ; et al. | 2014-05-08 |
Method and structure of forming backside through silicon via connections
Grant 8,709,936 - Volant , et al. April 29, 2 | 2014-04-29 |
TSV pillar as an interconnecting structure
Grant 8,691,691 - Farooq , et al. April 8, 2 | 2014-04-08 |
Leakage measurement structure having through silicon vias
Grant 8,692,246 - Bhoovaraghan , et al. April 8, 2 | 2014-04-08 |
Edge protection seal for bonded substrates
Grant 8,679,611 - Farooq , et al. March 25, 2 | 2014-03-25 |
Metal-contamination-free through-substrate via structure
Grant 8,679,971 - Farooq , et al. March 25, 2 | 2014-03-25 |
3D integrated circuits structure
Grant 8,674,515 - Farooq , et al. March 18, 2 | 2014-03-18 |
3-d Integration Using Multi Stage Vias
App 20140073134 - Farooq; Mukta G. ; et al. | 2014-03-13 |
Prevention Of Thru-substrate Via Pistoning Using Highly Doped Copper Alloy Seed Layer
App 20140061915 - Collins; Christopher N. ; et al. | 2014-03-06 |
Leakage Measurement Of Through Silicon Vias
App 20140065738 - Bhoovaraghan; Bhavana ; et al. | 2014-03-06 |
Method for fabricating 3D integrated circuit device using interface wafer as permanent carrier
Grant 8,664,081 - Farooq , et al. March 4, 2 | 2014-03-04 |
Semiconductor Device Having A Copper Plug
App 20140054778 - Farooq; Mukta G. ; et al. | 2014-02-27 |
Fluorine Depleted Adhesion Layer For Metal Interconnect Structure
App 20140038408 - Farooq; Mukta G. ; et al. | 2014-02-06 |
Fluorine Depleted Adhesion Layer For Metal Interconnect Structure
App 20140038407 - Farooq; Mukta G. ; et al. | 2014-02-06 |
Method And Structure Of Forming Backside Through Silicon Via Connections
App 20140035109 - Volant; Richard P. ; et al. | 2014-02-06 |
Sidewalls Of Electroplated Copper Interconnects
App 20140027296 - Farooq; Mukta G. ; et al. | 2014-01-30 |
Sidewalls Of Electroplated Copper Interconnects
App 20140027911 - Farooq; Mukta G. ; et al. | 2014-01-30 |
Sidewalls Of Electroplated Copper Interconnects
App 20140027912 - Farooq; Mukta G. ; et al. | 2014-01-30 |
Integrated void fill for through silicon via
Grant 8,633,580 - Volant , et al. January 21, 2 | 2014-01-21 |
3D integrated circuit device fabrication with precisely controllable substrate removal
Grant 8,629,553 - Farooq , et al. January 14, 2 | 2014-01-14 |
Polymeric edge seal for bonded substrates
Grant 8,613,996 - Farooq , et al. December 24, 2 | 2013-12-24 |
Sidewalls Of Electroplated Copper Interconnects
App 20130334691 - Farooq; Mukta G. ; et al. | 2013-12-19 |
Semiconductor device having a copper plug
Grant 8,610,283 - Farooq , et al. December 17, 2 | 2013-12-17 |
Integrated void fill for through silicon via
Grant 8,609,537 - Volant , et al. December 17, 2 | 2013-12-17 |
Via Structure For Three-Dimensional Circuit Integration
App 20130307160 - Farooq; Mukta G. ; et al. | 2013-11-21 |
Three dimensional integration and methods of through silicon via creation
Grant 8,586,431 - Farooq , et al. November 19, 2 | 2013-11-19 |
Three dimensional integration and methods of through silicon via creation
Grant 8,569,154 - Farooq , et al. October 29, 2 | 2013-10-29 |
Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
Grant 8,563,403 - Farooq , et al. October 22, 2 | 2013-10-22 |
Fluorine depleted adhesion layer for metal interconnect structure
Grant 8,563,423 - Farooq , et al. October 22, 2 | 2013-10-22 |
Bottom-up Plating Of Through-substrate Vias
App 20130260556 - Farooq; Mukta G. ; et al. | 2013-10-03 |
Alignment marks to enable 3D integration
Grant 8,546,961 - Farooq , et al. October 1, 2 | 2013-10-01 |
Optimized Annular Copper Tsv
App 20130244420 - Andry; Paul S. ; et al. | 2013-09-19 |
Simultaneously Forming A Through Silicon Via and a Deep Trench Structure
App 20130241034 - Cheng; Kangguo ; et al. | 2013-09-19 |
Three Dimensional Integration And Methods Of Through Silicon Via Creation
App 20130237054 - Farooq; Mukta G. ; et al. | 2013-09-12 |
Co-axial restraint for connectors within flip-chip packages
Grant 8,507,325 - Farooq , et al. August 13, 2 | 2013-08-13 |
3d Chip Stack Having Encapsulated Chip-in-chip
App 20130193574 - Farooq; Mukta G. ; et al. | 2013-08-01 |
Computer Readable Medium Encoded With A Program For Fabricating A 3d Integrated Circuit Structure
App 20130189813 - FAROOQ; Mukta G. ; et al. | 2013-07-25 |
3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
Grant 8,492,869 - Farooq , et al. July 23, 2 | 2013-07-23 |
Metal-contamination-free through-substrate via structure
Grant 8,492,878 - Farooq , et al. July 23, 2 | 2013-07-23 |
Method for simultaneously forming a through silicon via and a deep trench structure
Grant 8,492,241 - Cheng , et al. July 23, 2 | 2013-07-23 |
Three dimensional integration and methods of through silicon via creation
Grant 8,492,252 - Farooq , et al. July 23, 2 | 2013-07-23 |
Optimized annular copper TSV
Grant 8,487,425 - Andry , et al. July 16, 2 | 2013-07-16 |
Edge Protection Seal For Bonded Substrates
App 20130168017 - Farooq; Mukta G. ; et al. | 2013-07-04 |
Bonded Structure Employing Metal Semiconductor Alloy Bonding
App 20130171773 - Farooq; Mukta G. ; et al. | 2013-07-04 |
Non-conformal hardmask deposition for through silicon etch
Grant 8,476,168 - Graves-Abe , et al. July 2, 2 | 2013-07-02 |
Semiconductor Device Having A Copper Plug
App 20130157458 - Farooq; Mukta G. ; et al. | 2013-06-20 |
Grain refinement by precipitate formation in Pb-free alloys of tin
Grant 8,461,695 - Farooq June 11, 2 | 2013-06-11 |
Metal-contamination-free Through-substrate Via Structure
App 20130143400 - Farooq; Mukta G. ; et al. | 2013-06-06 |
3D multiple die stacking
Grant 8,455,270 - Farooq , et al. June 4, 2 | 2013-06-04 |
Integrated void fill for through silicon via
Grant 8,455,356 - Volant , et al. June 4, 2 | 2013-06-04 |
Soft error rate mitigation by interconnect structure
Grant 8,445,374 - Farooq , et al. May 21, 2 | 2013-05-21 |
Forming Beol Line Fuse Structure
App 20130119509 - FAROOQ; MUKTA G. ; et al. | 2013-05-16 |
Integrated Void Fill For Through Silicon Via
App 20130122702 - Volant; Richard P. ; et al. | 2013-05-16 |
Three dimensional integration and methods of through silicon via creation
Grant 8,415,238 - Farooq , et al. April 9, 2 | 2013-04-09 |
Leakage Measurement Of Through Silicon Vias
App 20130069062 - Bhoovaraghan; Bhavana ; et al. | 2013-03-21 |
Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer
Grant 8,399,336 - Farooq , et al. March 19, 2 | 2013-03-19 |
Three dimensional integration with through silicon vias having multiple diameters
Grant 8,399,180 - Farooq , et al. March 19, 2 | 2013-03-19 |
Method of fabricating coaxial through-silicon via
Grant 8,394,715 - Volant , et al. March 12, 2 | 2013-03-12 |
Circuit design checking for three dimensional chip technology
Grant 8,386,977 - Farooq , et al. February 26, 2 | 2013-02-26 |
Tsv Pillar As An Interconnecting Structure
App 20130026606 - Farooq; Mukta G. ; et al. | 2013-01-31 |
Optimized Annular Copper Tsv
App 20120326309 - ANDRY; PAUL S ; et al. | 2012-12-27 |
Method Of Forming A Through-silicon Via Utilizing A Metal Contact Pad In A Back-end-of-line Wiring Level To Fill The Through-silicon Via
App 20120315753 - Farooq; Mukta G. ; et al. | 2012-12-13 |
Method For Fabricating 3d Integrated Circuit Device Using Interface Wafer As Permanent Carrier
App 20120309127 - FAROOQ; Mukta G. ; et al. | 2012-12-06 |
3d Integrated Circuit Device Having Lower-cost Active Circuitry Layers Stacked Before Higher-cost Active Circuitry Layer
App 20120299200 - FAROOQ; Mukta G. ; et al. | 2012-11-29 |
Circuit Design Checking For Three Dimensional Chip Technology
App 20120304138 - Farooq; Mukta G. ; et al. | 2012-11-29 |
Integrated Void Fill For Through Silicon Via
App 20120292786 - Volant; Richard P. ; et al. | 2012-11-22 |
Edge Protection Seal For Bonded Substrates
App 20120288687 - Farooq; Mukta G. ; et al. | 2012-11-15 |
3-D Integration using Multi Stage Vias
App 20120280395 - Farooq; Mukta G. ; et al. | 2012-11-08 |
3D integrated circuit device fabrication using interface wafer as permanent carrier
Grant 8,298,914 - Farooq , et al. October 30, 2 | 2012-10-30 |
Enhanced electromigration resistance in TSV structure and design
Grant 8,288,270 - Farooq , et al. October 16, 2 | 2012-10-16 |
Edge protection seal for bonded substrates
Grant 8,287,980 - Farooq , et al. October 16, 2 | 2012-10-16 |
Method Of Fabricating Coaxial Through-silicon Via
App 20120258589 - Volant; Richard P. ; et al. | 2012-10-11 |
Co-axial Restraint For Connectors Within Flip-chip Packages
App 20120223434 - Farooq; Mukta G. ; et al. | 2012-09-06 |
Coaxial through-silicon via
Grant 8,242,604 - Volant , et al. August 14, 2 | 2012-08-14 |
Enhanced Electromigration Resistance In Tsv Structure And Design
App 20120199983 - Farooq; Mukta G. ; et al. | 2012-08-09 |
Enhanced Electromigration Resistance In Tsv Structure And Design
App 20120199975 - Farooq; Mukta G. ; et al. | 2012-08-09 |
Enhanced electromigration resistance in TSV structure and design
Grant 8,237,288 - Farooq , et al. August 7, 2 | 2012-08-07 |
Forming semiconductor chip connections
Grant 8,236,610 - Hsu , et al. August 7, 2 | 2012-08-07 |
Forming Semiconductor Chip Connections
App 20120187561 - Hsu; Louis Lu-Chen ; et al. | 2012-07-26 |
Three Dimensional Integration and Methods of Through Silicon Via Creation
App 20120190189 - Farooq; Mukta G. ; et al. | 2012-07-26 |
Non-conformal Hardmask Deposition For Through Silicon Etch
App 20120190204 - Graves-Abe; Troy L. ; et al. | 2012-07-26 |
Three Dimensional Integration and Methods of Through Silicon Via Creation
App 20120190196 - Farooq; Mukta G. ; et al. | 2012-07-26 |
Alignment Marks To Enable 3d Integration
App 20120175789 - Farooq; Mukta G. ; et al. | 2012-07-12 |
Semiconductor Device Having A Copper Plug
App 20120168952 - Farooq; Mukta G. ; et al. | 2012-07-05 |
Ionizing Radiation Blocking In Ic Chip To Reduce Soft Errors
App 20120161300 - Farooq; Mukta G. ; et al. | 2012-06-28 |
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal
App 20120153429 - FAROOQ; Mukta G. ; et al. | 2012-06-21 |
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal
App 20120149173 - Farooq; Mukta G. ; et al. | 2012-06-14 |
Soft Error Rate Mitigation By Interconnect Structure
App 20120135564 - Farooq; Mukta G. ; et al. | 2012-05-31 |
3d Integrated Circuits Structure
App 20120126425 - Farooq; Mukta G. ; et al. | 2012-05-24 |
GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN
App 20120119363 - Farooq; Mukta G. | 2012-05-17 |
Structure And Method For Simultaneously Forming A Through Silicon Via And A Deep Trench Structure
App 20120091593 - Cheng; Kangguo ; et al. | 2012-04-19 |
Method of making 3D integrated circuits
Grant 8,158,515 - Farooq , et al. April 17, 2 | 2012-04-17 |
3D integrated circuit device fabrication with precisely controllable substrate removal
Grant 8,129,256 - Farooq , et al. March 6, 2 | 2012-03-06 |
Grain refinement by precipitate formation in PB-free alloys of tin
Grant 8,128,868 - Farooq March 6, 2 | 2012-03-06 |
Soft error rate mitigation by interconnect structure
Grant 8,120,175 - Farooq , et al. February 21, 2 | 2012-02-21 |
Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
Grant 8,114,707 - Farooq , et al. February 14, 2 | 2012-02-14 |
Metal-contamination-free Through-substrate Via Structure
App 20120018851 - Farooq; Mukta G. ; et al. | 2012-01-26 |
Structure for inhibiting back end of line damage from dicing and chip packaging interaction failures
Grant 8,076,756 - Lane , et al. December 13, 2 | 2011-12-13 |
Fluorine Depleted Adhesion Layer For Metal Interconnect Structure
App 20110281432 - Farooq; Mukta G. ; et al. | 2011-11-17 |
Fluorine depleted adhesion layer for metal interconnect structure
Grant 8,039,964 - Farooq , et al. October 18, 2 | 2011-10-18 |
Method Of Forming A Multi-chip Stacked Structure Including A Thin Interposer Chip Having A Face-to-back Bonding With Another Chip
App 20110237026 - Farooq; Mukta G. ; et al. | 2011-09-29 |
Underbump metallurgy for enhanced electromigration resistance
Grant 8,022,543 - Farooq , et al. September 20, 2 | 2011-09-20 |
Vertical metal-insulator-metal (MIM) capacitor using gate stack, gate spacer and contact via
Grant 8,017,997 - Divakaruni , et al. September 13, 2 | 2011-09-13 |
Bonded Structure With Enhanced Adhesion Strength
App 20110193240 - Farooq; Mukta G. ; et al. | 2011-08-11 |
Structure And Method For Making Crack Stop For 3d Integrated Circuits
App 20110193197 - FAROOQ; MUKTA G. ; et al. | 2011-08-11 |
Co-axial Restraint For Connectors Within Flip-chip Packages
App 20110180920 - Farooq; Mukta G. ; et al. | 2011-07-28 |
Integrated Void Fill For Through Silicon Via
App 20110175216 - Volant; Richard P. ; et al. | 2011-07-21 |
3d Chip Stack Having Encapsulated Chip-in-chip
App 20110175215 - Farooq; Mukta G. ; et al. | 2011-07-21 |
Bonded Structure Employing Metal Semiconductor Alloy Bonding
App 20110168434 - Farooq; Mukta G. ; et al. | 2011-07-14 |
Three Dimensional Integration With Through Silicon Vias Having Multiple Diameters
App 20110171582 - Farooq; Mukta G. ; et al. | 2011-07-14 |
Three Dimensional Integration and Methods of Through Silicon Via Creation
App 20110171827 - Farooq; Mukta G. ; et al. | 2011-07-14 |
Structure For Inhibiting Back End Of Line Damage From Dicing And Chip Packaging Interaction Failures
App 20110140245 - LANE; MICHAEL W. ; et al. | 2011-06-16 |
Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures
Grant 7,955,955 - Lane , et al. June 7, 2 | 2011-06-07 |
3D integration structure and method using bonded metal planes
Grant 7,939,369 - Farooq , et al. May 10, 2 | 2011-05-10 |
Edge Protection Seal For Bonded Substrates
App 20110104426 - Farooq; Mukta G. ; et al. | 2011-05-05 |
Coaxial Through-silicon Via
App 20110095435 - Volant; Richard P. ; et al. | 2011-04-28 |
Polymeric Edge Seal For Bonded Substrates
App 20110091685 - Farooq; Mukta G. ; et al. | 2011-04-21 |
BLM structure for application to copper pad
Grant 7,923,836 - Farooq , et al. April 12, 2 | 2011-04-12 |
Semiconductor Device Having A Copper Plug
App 20110079907 - FAROOQ; MUKTA G. ; et al. | 2011-04-07 |
Method and structure to reduce cracking in flip chip underfill
Grant 7,919,356 - Farooq , et al. April 5, 2 | 2011-04-05 |
3d Multiple Die Stacking
App 20110065214 - Farooq; Mukta G. ; et al. | 2011-03-17 |
Solder interconnection array with optimal mechanical integrity
Grant 7,900,809 - Daves , et al. March 8, 2 | 2011-03-08 |
Apparatus for removing interconnects to separate two parts of a workpiece
Grant 7,882,623 - Farooq , et al. February 8, 2 | 2011-02-08 |
Structure and method for enhancing resistance to fracture of bonding pads
Grant 7,867,887 - Melville , et al. January 11, 2 | 2011-01-11 |
Method of making a sidewall-protected metallic pillar on a semiconductor substrate
Grant 7,855,137 - Farooq , et al. December 21, 2 | 2010-12-21 |
3d Integrated Circuit Device Having Lower-cost Active Circuitry Layers Stacked Before Higher-cost Active Circuitry Layer
App 20100314711 - Farooq; Mukta G. ; et al. | 2010-12-16 |
Forming Semiconductor Chip Connections
App 20100301475 - Hsu; Louis Lu-Chen ; et al. | 2010-12-02 |
3d Integration Structure And Method Using Bonded Metal Planes
App 20100289144 - Farooq; Mukta G. ; et al. | 2010-11-18 |
Three Dimensional Integrated Circuit Integration Using Dielectric Bonding First And Through Via Formation Last
App 20100264551 - FAROOQ; MUKTA G. ; et al. | 2010-10-21 |
GRAIN REFINEMENT BY PRECIPITATE FORMATION IN Pb-FREE ALLOYS OF TIN
App 20100200988 - FAROOQ; Mukta G. | 2010-08-12 |
Method Of Making 3d Integrated Circuits And Structures Formed Thereby
App 20100193964 - Farooq; Mukta G. ; et al. | 2010-08-05 |
Vertical Metal-insulator-metal (mim) Capacitor Using Gate Stack, Gate Spacer And Contact Via
App 20100163949 - Divakaruni; Ramachandra ; et al. | 2010-07-01 |
STRUCTURE AND METHOD TO GAIN SUBSTANTIAL RELIABILITY IMPROVEMENTS IN LEAD-FREE BGAs ASSEMBLED WITH LEAD-BEARING SOLDERS
App 20100139958 - Farooq; Mukta G. ; et al. | 2010-06-10 |
3d Integrated Circuit Device Fabrication With Precisely Controllable Substrate Removal
App 20100044826 - FAROOQ; Mukta G. ; et al. | 2010-02-25 |
3d Integrated Circuit Device Fabrication Using Interface Wafer As Permanent Carrier
App 20100047964 - FAROOQ; Mukta G. ; et al. | 2010-02-25 |
Method Of Making A Sidewall-protected Metallic Pillar On A Semiconductor Substrate
App 20100038777 - Farooq; Mukta G. ; et al. | 2010-02-18 |
Semiconductor Chip Shape Alteration
App 20100019354 - Farooq; Mukta G. ; et al. | 2010-01-28 |
Underbump Metallurgy For Enhanced Electromigration Resistance
App 20090243098 - Farooq; Mukta G. ; et al. | 2009-10-01 |
Fluorine Depleted Adhesion Layer For Metal Interconnect Structure
App 20090212439 - Farooq; Mukta G. ; et al. | 2009-08-27 |
Inhibition Of Metal Diffusion Arising From Laser Dicing
App 20090155983 - FAROOQ; MUKTA G. ; et al. | 2009-06-18 |
Inhibition of Metal Diffusion Arising from Laser Dicing
App 20090155985 - Farooq; Mukta G. ; et al. | 2009-06-18 |
Wire Bonding Personalization And Discrete Component Attachment On Wirebond Pads
App 20090146321 - Beaulieu; Frederic ; et al. | 2009-06-11 |
Structure For Implementing Secure Multichip Modules For Encryption Applications
App 20090145973 - Farooq; Mukta G. ; et al. | 2009-06-11 |
Pad Structure To Provide Improved Stress Relief
App 20090140432 - Farooq; Mukta G. ; et al. | 2009-06-04 |
Soft Error Rate Mitigation By Interconnect Structure
App 20090140420 - Farooq; Mukta G. ; et al. | 2009-06-04 |
Self-assembled Stress Relief Interface
App 20090108442 - Fitzsimmons; John A. ; et al. | 2009-04-30 |
Ionizing Radiation Blocking In Ic Chip To Reduce Soft Errors
App 20090039515 - Farooq; Mukta G. ; et al. | 2009-02-12 |
Method And Structure To Reduce Cracking In Flip Chip Underfill
App 20090032974 - Farooq; Mukta G. ; et al. | 2009-02-05 |
Test Structures For Electrically Detecting Back End Of The Line Failures And Methods Of Making And Using The Same
App 20090015285 - Farooq; Mukta G. ; et al. | 2009-01-15 |
Inhibiting Damage From Dicing And Chip Packaging Interaction Failures In Back End Of Line Structures
App 20080277765 - Lane; Michael W. ; et al. | 2008-11-13 |
Ball Grid Array Rework Using A Continuous Belt Furnace
App 20080271312 - Farooq; Mukta G. ; et al. | 2008-11-06 |
Structure And Method For Enhancing Resistance To Fracture Of Bonding Pads
App 20080274608 - Melville; Ian D. ; et al. | 2008-11-06 |
Solder Interconnection Array With Optimal Mechanical Integrity
App 20080261350 - Daves; Glenn G. ; et al. | 2008-10-23 |
Solder Connector Structure And Method
App 20080248643 - Farooq; Mukta G. ; et al. | 2008-10-09 |
Techniques For Forming Interconnects
App 20080175939 - Danovitch; David H. ; et al. | 2008-07-24 |
Semiconductor Chip Shape Alteration
App 20080150087 - Farooq; Mukta G. ; et al. | 2008-06-26 |
Structure And Method For Enhancing Resistance To Fracture Of Bonding Pads
App 20080111250 - Melville; Ian D. ; et al. | 2008-05-15 |
Methods Of Forming Aluminum-free Wire Bond Pad And Pad So Formed
App 20080038913 - Farooq; Mukta G. ; et al. | 2008-02-14 |
Via Stack Structures
App 20080029898 - Farooq; Mukta G. ; et al. | 2008-02-07 |
Solder Connector Structure And Method
App 20080023827 - Farooq; Mukta G. ; et al. | 2008-01-31 |
Blm Structure For Application To Copper Pad
App 20080017984 - Farooq; Mukta G. ; et al. | 2008-01-24 |
Compressible Films Surrounding Solder Connectors
App 20080009101 - Bernier; William E. ; et al. | 2008-01-10 |
Method And Structure For Implementing Secure Multichip Modules For Encryption Applications
App 20080000988 - Farooq; Mukta G. ; et al. | 2008-01-03 |
Compliant Electrical Contacts
App 20080000080 - Bernier; William E. ; et al. | 2008-01-03 |
Ball Grid Array Rework Using A Continuous Belt Furnace
App 20070271775 - Farooq; Mukta G. ; et al. | 2007-11-29 |
Semiconductor Module And Method For Forming The Same
App 20070252288 - FAROOQ; MUKTA G. ; et al. | 2007-11-01 |
Method For Forming C4 Connections On Integrated Circuit Chips And The Resulting Devices
App 20070252274 - Daubenspeck; Timothy H. ; et al. | 2007-11-01 |
STRUCTURE AND METHOD TO GAIN SUBSTANTIAL RELIABILITY IMPROVEMENTS IN LEAD-FREE BGAs ASSEMBLED WITH LEAD-BEARING SOLDERS
App 20070228117 - Farooq; Mukta G. ; et al. | 2007-10-04 |
Method And Structure For Eliminating Aluminum Terminal Pad Material In Semiconductor Devices
App 20070232049 - Edelstein; Daniel C. ; et al. | 2007-10-04 |
Ild Layer With Intermediate Dielectric Constant Material Immediately Below Silicon Dioxide Based Ild Layer
App 20070187828 - Farooq; Mukta G. ; et al. | 2007-08-16 |
Composite Interconnect Structure Using Injection Molded Solder Technique
App 20070178625 - Danovitch; David D. ; et al. | 2007-08-02 |
Low Stress Conductive Polymer Bump
App 20070084629 - Bernier; William E. ; et al. | 2007-04-19 |
Structure And Method For Producing Multiple Size Interconnections
App 20070007665 - Clevenger; Lawrence ; et al. | 2007-01-11 |
| 