loadpatents
name:-0.022958993911743
name:-0.019965887069702
name:-0.0019769668579102
Fanning; Blaise B. Patent Filings

Fanning; Blaise B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fanning; Blaise B..The latest application filed is for "method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device".

Company Profile
0.15.14
  • Fanning; Blaise B. - El Dorado Hills CA
  • Fanning, Blaise B. - Folsom CA
  • Fanning; Blaise B. - El Dorado Hils CA
  • Fanning; Blaise B. - Cameron Park CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
Grant 7,313,653 - Fanning December 25, 2
2007-12-25
Dedicated cache memory
Grant 7,213,107 - Fanning May 1, 2
2007-05-01
Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
App 20060117144 - Fanning; Blaise B.
2006-06-01
Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
Grant 7,017,008 - Fanning March 21, 2
2006-03-21
Bounding data transmission latency based upon link loading and arrangement
App 20050259579 - Fanning, Blaise B.
2005-11-24
Multi-threaded processing of system management interrupts
Grant 6,968,410 - Bennett , et al. November 22, 2
2005-11-22
Point-to-point busing and arrangement
Grant 6,918,001 - Fanning July 12, 2
2005-07-12
Bounding data transmission latency based upon link loading and arrangement
Grant 6,918,060 - Fanning July 12, 2
2005-07-12
Dedicated cache memory
App 20050144393 - Fanning, Blaise B.
2005-06-30
Arbitration of asynchronous and isochronous requests
App 20050138251 - Fanning, Blaise B.
2005-06-23
Controlling cache memory in external chipset using processor
Grant 6,904,499 - Fanning June 7, 2
2005-06-07
Bounding data transmission latency based upon a data transmission event and arrangement
Grant 6,880,111 - Fanning April 12, 2
2005-04-12
Method and mechanism for common scheduling in a RDRAM system
Grant 6,684,311 - Fanning January 27, 2
2004-01-27
Circuit and system for DRAM refresh with scoreboard methodology
Grant 6,650,586 - Fanning November 18, 2
2003-11-18
Cache line replacement policy enhancement to avoid memory page thrashing
Grant 6,625,695 - Fanning September 23, 2
2003-09-23
Method and apparatus for regulating write burst lengths
Grant 6,615,308 - Fanning September 2, 2
2003-09-02
Method for dynamically adjusting memory system paging policy
Grant 6,604,186 - Fanning August 5, 2
2003-08-05
Point-to-point busing and arrangement
App 20030135682 - Fanning, Blaise B.
2003-07-17
Cache Line Replacement Policy Enhancement To Avoid Memory Page Thrashing
App 20030093644 - Fanning, Blaise B.
2003-05-15
Bounding data transmission latency based upon a data transmission event and arrangement
App 20030084029 - Fanning, Blaise B.
2003-05-01
Bounding data transmission latency based upon link loading and arrangement
App 20030081558 - Fanning, Blaise B.
2003-05-01
Cache line replacement policy enhancement to avoid memory page thrashing
Grant 6,523,092 - Fanning February 18, 2
2003-02-18
Method and mechanism for common scheduling in a RDRAM system
App 20020199072 - Fanning, Blaise B.
2002-12-26
Controlling cache memory in external chipset using processor
App 20020144064 - Fanning, Blaise B.
2002-10-03
Prefetch canceling based on most recent accesses
App 20020144054 - Fanning, Blaise B. ;   et al.
2002-10-03
Technique for capturing information
App 20020120801 - Bennett, Joseph A. ;   et al.
2002-08-29
Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device
App 20020087796 - Fanning, Blaise B.
2002-07-04
System and method for efficient BIOS initialization
App 20020069352 - Fanning, Blaise B.
2002-06-06
Method and apparatus for dynamically changing the sizes of pools that control the power consumption levels of memory devices
Grant 6,330,639 - Fanning , et al. December 11, 2
2001-12-11

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