loadpatents
name:-0.012187957763672
name:-0.0075619220733643
name:-0.00070691108703613
Fang; Yung-Sheng Patent Filings

Fang; Yung-Sheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fang; Yung-Sheng.The latest application filed is for "physical analysis method, sample for physical analysis and preparing method thereof".

Company Profile
0.9.10
  • Fang; Yung-Sheng - Hsinchu TW
  • FANG; YUNG-SHENG - Hsinchu City TW
  • Fang; Yung-Sheng - Kaohsiung TW
  • Fang; Yung-Sheng - Kaohsiung City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Electronic system, integrated circuit die and operation method thereof
Grant 11,411,560 - Yu , et al. August 9, 2
2022-08-09
Circuit For Providing Clock To De-serializer In Communication Physical Layer
App 20220221893 - Wang; Ting-Hao ;   et al.
2022-07-14
Physical Analysis Method, Sample For Physical Analysis And Preparing Method Thereof
App 20220223373 - WU; CHIEN-WEI ;   et al.
2022-07-14
Data Protection System And Method Thereof For 3d Semiconductor Device
App 20220058155 - Elkanovich; Igor ;   et al.
2022-02-24
Interface For Semiconductor Device And Interfacing Method Thereof
App 20220058144 - Elkanovich; Igor ;   et al.
2022-02-24
Semiconductor Device In 3d Stack With Communication Interface And Managing Method Thereof
App 20220059501 - Elkanovich; Igor ;   et al.
2022-02-24
Interface for semiconductor device with symmetric bond pattern and method for arranging interface thereof
Grant 11,144,485 - Elkanovich , et al. October 12, 2
2021-10-12
Frame decoding circuit and method for performing frame decoding
Grant 11,063,596 - Wang , et al. July 13, 2
2021-07-13
Interface device and interface method for 3D semiconductor device
Grant 11,031,923 - Elkanovich , et al. June 8, 2
2021-06-08
Electronic device, performance binning system and method, voltage automatic calibration system
Grant 10,145,896 - Chen , et al. De
2018-12-04
Method of optimizing the width of transaction ID for an interconnecting bus
Grant 9,304,959 - Liao , et al. April 5, 2
2016-04-05
Method of determining performance of a chip of an integrated-circuit design and an apparatus and an integrated circuit using the same
Grant 9,244,122 - Chen , et al. January 26, 2
2016-01-26
Electronic Device, Performance Binning System And Method, Voltage Automatic Calibration System
App 20150226790 - CHEN; Shi-Hao ;   et al.
2015-08-13
Method Of Optimizing The Width Of Transaction Id For An Interconnecting Bus
App 20150052271 - Liao; Ying-Ze ;   et al.
2015-02-19
Method And An Apparatus Of Determining Performance Of An Integrated Circuit
App 20150042369 - Chen; Shi-Hao ;   et al.
2015-02-12

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