loadpatents
name:-0.019257068634033
name:-0.01855206489563
name:-0.0015571117401123
Fan; Jiewen Patent Filings

Fan; Jiewen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fan; Jiewen.The latest application filed is for "method for preparing a nano-scale field-effect transistor".

Company Profile
0.28.25
  • Fan; Jiewen - Beijing CN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integration method for a vertical nanowire transistor
Grant 9,502,310 - Li , et al. November 22, 2
2016-11-22
Method for fabricating FinFET with separated double gates on bulk silicon
Grant 9,478,641 - Huang , et al. October 25, 2
2016-10-25
Method For Preparing A Nano-scale Field-effect Transistor
App 20160268384 - Li; Ming ;   et al.
2016-09-15
Method For Fabricating A Quasi-soi Source-drain Multi-gate Device
App 20160247726 - HUANG; Ru ;   et al.
2016-08-25
Method for fabricating multiple layers of ultra narrow silicon wires
Grant 9,425,060 - Li , et al. August 23, 2
2016-08-23
Semiconductor Structure And Method For Forming The Same
App 20160225851 - LI; Ming ;   et al.
2016-08-04
Method of adjusting a threshold voltage of a multi-gate structure device
Grant 9,396,949 - Li , et al. July 19, 2
2016-07-19
Method for Fabricating Multiple Layers of Ultra Narrow Silicon Wires
App 20160181114 - Li; Ming ;   et al.
2016-06-23
Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure
Grant 9,356,124 - Huang , et al. May 31, 2
2016-05-31
Method for fabricating quasi-SOI source/drain field effect transistor device
Grant 9,349,588 - Huang , et al. May 24, 2
2016-05-24
Method For Fabricating Quasi-soi Source/drain Field Effect Transistor Device
App 20160118245 - Huang; Ru ;   et al.
2016-04-28
Method For Fabricating Multi-gate Structure Device With Source And Drain Having Quasi-soi Structure
App 20160064529 - HUANG; Ru ;   et al.
2016-03-03
Method For Fabricating Finfet With Separated Double Gates On Bulk Silicon
App 20150236130 - Huang; Ru ;   et al.
2015-08-20
Programmable array of silicon nanowire field effect transistor and method for fabricating the same
Grant 9,099,500 - Huang , et al. August 4, 2
2015-08-04
Method Of Adjusting A Threshold Voltage Of A Multi-gate Structure Device
App 20150206752 - Li; Ming ;   et al.
2015-07-23
Method For Fabricating Finfet On Germanium Or Group Iii-v Semiconductor Substrate
App 20150140758 - Huang; Ru ;   et al.
2015-05-21
Method for fabricating silicon nanowire field effect transistor based on wet etching
Grant 9,034,702 - Huang , et al. May 19, 2
2015-05-19
Method for testing density and location of gate dielectric layer trap of semiconductor device
Grant 9,018,968 - Huang , et al. April 28, 2
2015-04-28
Field effect transistor with a vertical channel and fabrication method thereof
Grant 8,901,644 - Huang , et al. December 2, 2
2014-12-02
Method for testing trap density of gate dielectric layer in semiconductor device having no substrate contact
Grant 8,866,507 - Huang , et al. October 21, 2
2014-10-21
Method for fabricating semiconductor nano circular ring
Grant 8,722,312 - Huang , et al. May 13, 2
2014-05-13
Fabrication method of vertical silicon nanowire field effect transistor
Grant 8,592,276 - Huang , et al. November 26, 2
2013-11-26
High voltage-resistant lateral double-diffused transistor based on nanowire device
Grant 8,564,031 - Huang , et al. October 22, 2
2013-10-22
Method for fabricating surrounding-gate silicon nanowire transistor with air sidewalls
Grant 8,563,370 - Huang , et al. October 22, 2
2013-10-22
Method For Testing Density And Location Of Gate Dielectric Layer Trap Of Semiconductor Device
App 20130214810 - Huang; Ru ;   et al.
2013-08-22
Fabrication method for surrounding gate silicon nanowire transistor with air as spacers
Grant 8,513,067 - Huang , et al. August 20, 2
2013-08-20
Field Effect Transistor With A Vertical Channel And Fabrication Method Thereof
App 20130168759 - Huang; Ru ;   et al.
2013-07-04
Method For Fabricating Ultra-fine Nanowire
App 20130130503 - Huang; Ru ;   et al.
2013-05-23
Programmable Array Of Silicon Nanowire Field Effect Transistor And Method For Fabricating The Same
App 20130075701 - Huang; Ru ;   et al.
2013-03-28
Method for fabricating ultra-fine nanowire
Grant 8,372,752 - Huang , et al. February 12, 2
2013-02-12
Fabrication Method For Surrounding Gate Silicon Nanowire Transistor With Air As Spacers
App 20130017654 - Huang; Ru ;   et al.
2013-01-17
Fabrication Method Of Vertical Silicon Nanowire Field Effect Transistor
App 20130011980 - Huang; Ru ;   et al.
2013-01-10
Method For Fabricating Surrounding-gate Silicon Nanowire Transistor With Air Sidewalls
App 20120302014 - Huang; Ru ;   et al.
2012-11-29
Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching
App 20120302027 - Huang; Ru ;   et al.
2012-11-29
High Voltage-resistant Lateral Double-diffused Transistor Based On Nanowire Device
App 20120199808 - Huang; Ru ;   et al.
2012-08-09
Method For Testing Trap Density Of Gate Dielectric Layer In Semiconductor Device Having No Substrate Contact
App 20120187976 - Huang; Ru ;   et al.
2012-07-26
Method For Fabricating Semiconductor Nano Circular Ring
App 20120190202 - Huang; Ru ;   et al.
2012-07-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed