FAN; FANG-YU

Patent Applications and Registrations

Patent applications and USPTO patent grants for FAN; FANG-YU.The latest application filed is for "fishbone structure enhancing spacing with adjacent conductive line in power network".

Company Profile

0.13.13

FAN; FANG-YU - HSINCHU COUNTY TW
Fan; Fang-Yu - Hukou Township, Hsinchu County N/A TW
Fan; Fang-Yu - Hukou Township TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fishbone Structure Enhancing Spacing With Adjacent Conductive Line In Power Network App 20220139826 - CHAO; CHIEN-JU ; et al.	2022-05-05
Fishbone structure enhancing spacing with adjacent conductive line in power network Grant 11,239,154 - Chao , et al. February 1, 2	2022-02-01
Semiconductor device with self-aligned interconnects Grant 9,627,310 - Chang , et al. April 18, 2	2017-04-18
Interconnect structure having smaller transition layer via Grant 9,553,043 - Lu , et al. January 24, 2	2017-01-24
Fishbone Structure Enhancing Spacing With Adjacent Conductive Line In Power Network App 20160211212 - CHAO; CHIEN-JU ; et al.	2016-07-21
Double patterning technology (DPT) layout routing Grant 9,317,650 - Chen , et al. April 19, 2	2016-04-19
Cell layout design and method Grant 9,087,170 - Hsu , et al. July 21, 2	2015-07-21
Cell Layout Design And Method App 20150067616 - HSU; Chin-Hsiung ; et al.	2015-03-05
Double Patterning Technology (dpt) Layout Routing App 20150012895 - Chen; Huang-Yu ; et al.	2015-01-08
Semiconductor device with self-aligned interconnects and blocking portions Grant 8,907,497 - Chang , et al. December 9, 2	2014-12-09
Double patterning technology (DPT) layout routing Grant 8,850,368 - Chen , et al. September 30, 2	2014-09-30
Double Patterning Technology (dpt) Layout Routing App 20140215428 - Chen; Huang-Yu ; et al.	2014-07-31
Semiconductor Device With Self-Aligned Interconnects and Blocking Portions App 20130285246 - Chang; Shih-Ming ; et al.	2013-10-31
Semiconductor Device with Self-Aligned Interconnects App 20130270704 - Chang; Shih-Ming ; et al.	2013-10-17
Interconnect Structure Having Smaller Transition Layer Via App 20130256902 - LU; Lee-Chung ; et al.	2013-10-03
Method and apparatus for achieving multiple patterning technology compliant design layout Grant 8,418,111 - Chen , et al. April 9, 2	2013-04-09
Double patterning technology using single-patterning-spacer-technique Grant 8,211,807 - Chen , et al. July 3, 2	2012-07-03
Method And Apparatus For Achieving Multiple Patterning Technology Compliant Design Layout App 20120131528 - Chen; Huang-Yu ; et al.	2012-05-24
Double Patterning Technology Using Single-Patterning-Spacer-Technique App 20120091592 - Chen; Huang-Yu ; et al.	2012-04-19

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