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name:-0.0055270195007324
name:-0.016080141067505
name:-0.0025060176849365
Fallon; Elias Patent Filings

Fallon; Elias

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fallon; Elias.The latest application filed is for "analog layout module generator and method".

Company Profile
0.5.3
  • Fallon; Elias - Allison Park PA
  • Fallon; Elias - Pittsburgh PA
  • Fallon; Elias - Tempe AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effects
Grant 8,732,640 - Krishnan , et al. May 20, 2
2014-05-20
Analog layout module generator and method
Grant 7,543,262 - Wang , et al. June 2, 2
2009-06-02
Analog layout module generator and method
App 20070130553 - Wang; Zhigang ;   et al.
2007-06-07
Method for generating constrained component placement for integrated circuits and packages
Grant 7,093,220 - Fallon , et al. August 15, 2
2006-08-15
Integrated circuit design layout compaction method
Grant 6,874,133 - Gopalakrishnan , et al. March 29, 2
2005-03-29
Method for generating constrained component placement for integrated circuits and packages
App 20050028122 - Fallon, Elias ;   et al.
2005-02-03
Integrated circuit design layout compaction method
App 20040111682 - Gopalakrishnan, Prakash ;   et al.
2004-06-10

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