loadpatents
name:-0.036839962005615
name:-0.024190902709961
name:-0.015336036682129
Fachmann; Christian Patent Filings

Fachmann; Christian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fachmann; Christian.The latest application filed is for "method for forming an insulation layer in a semiconductor body and transistor device".

Company Profile
14.23.31
  • Fachmann; Christian - Fuernitz AT
  • Fachmann; Christian - Furnitz AT
  • Fachmann; Christian - Dresden DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of manufacturing a superjunction semiconductor device
Grant 11,329,126 - Tilke , et al. May 10, 2
2022-05-10
Method for Forming an Insulation Layer in a Semiconductor Body and Transistor Device
App 20220077309 - Weber; Hans ;   et al.
2022-03-10
Chip-substrate Composite Semiconductor Device
App 20220028699 - Fachmann; Christian ;   et al.
2022-01-27
Power Relay Circuit
App 20210407746 - Muri; Ingo ;   et al.
2021-12-30
Method for forming an insulation layer in a semiconductor body and transistor device
Grant 11,211,483 - Weber , et al. December 28, 2
2021-12-28
Multi-Die-Package and Method
App 20210335696 - Riegler; Andreas ;   et al.
2021-10-28
Power relay circuit
Grant 11,139,125 - Muri , et al. October 5, 2
2021-10-05
Method for operating a superjunction transistor device
Grant 11,088,275 - Weber , et al. August 10, 2
2021-08-10
Multi-die-package and method
Grant 11,081,430 - Riegler , et al. August 3, 2
2021-08-03
Semiconductor Device
App 20200388703 - Hirler; Franz ;   et al.
2020-12-10
Transistor device with gate resistor
Grant 10,811,529 - Riegler , et al. October 20, 2
2020-10-20
Method for Operating a Superjunction Transistor Device
App 20200287535 - Weber; Hans ;   et al.
2020-09-10
Power Relay Circuit
App 20200161062 - Muri; Ingo ;   et al.
2020-05-21
Charge compensation semiconductor devices
Grant 10,651,271 - Tutuc , et al.
2020-05-12
Method for Forming an Insulation Layer in a Semiconductor Body and Transistor Device
App 20200105918 - Weber; Hans ;   et al.
2020-04-02
Semiconductor Oxide or Glass Based Connection Body with Wiring Structure
App 20200091058 - Riegler; Andreas ;   et al.
2020-03-19
Transistor Device with Gate Resistor
App 20190319124 - Riegler; Andreas ;   et al.
2019-10-17
Semiconductor device having a first through contact structure in ohmic contact with the gate electrode
Grant 10,411,126 - Riegler , et al. Sept
2019-09-10
Field-effect semiconductor device having N and P-doped pillar regions
Grant 10,374,032 - Weber , et al.
2019-08-06
Multi-Die-Package and Method
App 20190157191 - Riegler; Andreas ;   et al.
2019-05-23
Charge Compensation Semiconductor Devices
App 20190123137 - Tutuc; Daniel ;   et al.
2019-04-25
Superjunction semiconductor device having a superstructure
Grant 10,224,394 - Weber , et al.
2019-03-05
Field-Effect Semiconductor Device and a Manufacturing Method Therefor
App 20190051742 - Riegler; Andreas ;   et al.
2019-02-14
Method of Manufacturing a Superjunction Semiconductor Device
App 20180374919 - Tilke; Armin ;   et al.
2018-12-27
Charge compensation semiconductor devices
Grant 10,157,982 - Tutuc , et al. Dec
2018-12-18
Field-Effect Semiconductor Device and a Manufacturing Method Therefor
App 20180294333 - Weber; Hans ;   et al.
2018-10-11
Superjunction Semiconductor Device Having a Superstructure
App 20180158901 - Weber; Hans ;   et al.
2018-06-07
Charge Compensation Semiconductor Devices
App 20180061937 - Tutuc; Daniel ;   et al.
2018-03-01
Method of manufacturing superjunction semiconductor devices with a superstructure in alignment with a foundation
Grant 9,905,639 - Weber , et al. February 27, 2
2018-02-27
Semiconductor package with top side cooling heat sink thermal pathway
Grant 9,812,373 - Fachmann , et al. November 7, 2
2017-11-07
Intermediate layer for copper structuring and methods of formation thereof
Grant 9,773,736 - Joshi , et al. September 26, 2
2017-09-26
Semiconductor device having switchable regions with different transconductances
Grant 9,679,895 - Fachmann , et al. June 13, 2
2017-06-13
Method of Manufacturing Superjunction Semiconductor Devices with a Superstructure in Alignment with a Foundation
App 20170154956 - Weber; Hans ;   et al.
2017-06-01
Method for manufacturing a semiconductor switching device with different local cell geometry
Grant 9,583,395 - Fachmann , et al. February 28, 2
2017-02-28
Intermediate Layer for Copper Structuring and Methods of Formation Thereof
App 20160218033 - Joshi; Ravi Keshav ;   et al.
2016-07-28
Semiconductor Device Having Switchable Regions with Different Transconductances
App 20160190125 - Fachmann; Christian ;   et al.
2016-06-30
Heat Spreader, Electronic Module Comprising a Heat Spreader and Method of Fabrication Thereof
App 20160163616 - Fachmann; Christian ;   et al.
2016-06-09
Semiconductor switching device with different local threshold voltage
Grant 9,349,795 - Fachmann , et al. May 24, 2
2016-05-24
Layer arrangement
Grant 9,349,794 - Trichy Rengarajan , et al. May 24, 2
2016-05-24
Method for Manufacturing a Semiconductor Switching Device with Different Local Cell Geometry
App 20160099180 - Fachmann; Christian ;   et al.
2016-04-07
Semiconductor switching devices with different local transconductance
Grant 9,293,533 - Fachmann , et al. March 22, 2
2016-03-22
Semiconductor switching device with different local cell geometry
Grant 9,231,049 - Fachmann , et al. January 5, 2
2016-01-05
Semiconductor Switching Device with Different Local Cell Geometry
App 20150372076 - Fachmann; Christian ;   et al.
2015-12-24
Semiconductor Switching Device with Different Local Threshold Voltage
App 20150372086 - Fachmann; Christian ;   et al.
2015-12-24
Semiconductor Switching Devices with Different Local Transconductance
App 20150372087 - Fachmann; Christian ;   et al.
2015-12-24
Layer Arrangement
App 20140264764 - TRICHY RENGARAJAN; Gopalakrishnan ;   et al.
2014-09-18
Method for manufacturing a layer arrangement, and a layer arrangement
Grant 8,772,948 - Trichy Rengarajan , et al. July 8, 2
2014-07-08
Method For Manufacturing A Layer Arrangement, And A Layer Arrangement
App 20140061935 - TRICHY RENGARAJAN; Gopalakrishnan ;   et al.
2014-03-06
Semiconductor device
Grant 8,097,944 - Landau , et al. January 17, 2
2012-01-17
Semiconductor Device
App 20100276797 - Landau; Stefan ;   et al.
2010-11-04
Device Including An Imide Layer With Non-contact Openings And Method
App 20100007028 - Fachmann; Christian ;   et al.
2010-01-14
Selective deposition method
App 20080242097 - Boescke; Tim ;   et al.
2008-10-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed