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Scheduler Queue Assignment Burst Mode
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Selectively Performing Ahead Branch Prediction Based On Types Of Branch Instructions
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Low latency synchronization for operation cache and instruction cache fetching and decoding instructions
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Processor With Accelerated Lock Instruction Operation
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Selectively performing ahead branch prediction based on types of branch instructions
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Stride prefetching across memory pages
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Branch Target Buffer With Early Return Prediction
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Low Latency Synchronization For Operation Cache And Instruction Cache Fetching And Decoding Instructions
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Selectively Performing Ahead Branch Prediction Based On Types Of Branch Instructions
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Storing Incidental Branch Predictions To Reduce Latency Of Misprediction Recovery
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Tracking Stores And Loads By Bypassing Load Store Units
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Retaining Cache Entries Of A Processor Core During A Powered-down State
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Bandwidth increase in branch prediction unit and level 1 instruction cache
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Method and apparatus for performing a bus lock and translation lookaside buffer invalidation
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Resource management for northbridge using tokens
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Variable distance bypass between tag array and data array pipelines in a cache
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Dynamic evaluation and reconfiguration of a data prefetcher
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Bandwidth Increase In Branch Prediction Unit And Level 1 Instruction Cache
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Method And Apparatus For Performing A Bus Lock And Translation Lookaside Buffer Invalidation
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Ordering And Bandwidth Improvements For Load And Store Unit And Data Cache
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Stride Prefetching Across Memory Pages
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Resource Management For Northbridge Using Tokens
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