Estabil; Jose J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Estabil; Jose J..The latest application filed is for "contactless technique for evaluating a fabrication of a wafer".

Company Profile

0.11.11

Estabil; Jose J. - Weston CT US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Contactless technique for evaluating a fabrication of a wafer Grant 8,990,759 - Aghababazadeh , et al. March 24, 2	2015-03-24
Test structures for evaluating a fabrication of a die or a wafer Grant 8,344,745 - Aghababazadeh , et al. January 1, 2	2013-01-01
Contactless Technique For Evaluating A Fabrication Of A Wafer App 20100304509 - Aghababazadeh; Majid ; et al.	2010-12-02
System and apparatus for using test structures inside of a chip during the fabrication of the chip Grant 7,736,916 - Aghababazadeh , et al. June 15, 2	2010-06-15
Contactless technique for evaluating a fabrication of a wafer Grant 7,730,434 - Aghababazadeh , et al. June 1, 2	2010-06-01
System for using test structures to evaluate a fabrication of a wafer Grant 7,723,724 - Aghababazadeh , et al. May 25, 2	2010-05-25
Intra-chip power and test signal generation for use with test structures on wafers Grant 7,605,597 - Aghababazadeh , et al. October 20, 2	2009-10-20
Technique For Evaluating A Fabrication Of A Die And Wafer App 20080315196 - AGHABABAZADEH; Majid ; et al.	2008-12-25
Technique for evaluating a fabrication of a die and wafer Grant 7,423,288 - Aghababazadeh , et al. September 9, 2	2008-09-09
Intra-chip Power And Test Signal Generation For Use With Test Structures On Wafers App 20080100319 - Aghababazadeh; Majid ; et al.	2008-05-01
Intra-clip power and test signal generation for use with test structures on wafers Grant 7,339,388 - Aghababazadeh , et al. March 4, 2	2008-03-04
System And Apparatus For Using Test Structures Inside Of A Chip During The Fabrication Of The Chip App 20070238206 - Aghababazadeh; Majid ; et al.	2007-10-11
System And Apparatus For Using Test Structures Inside Of A Chip During The Fabrication Of The Chip App 20070236232 - Aghababazadeh; Majid ; et al.	2007-10-11
Technique For Evaluating A Fabrication Of A Die And Wafer App 20070187679 - Aghababazadeh; Majid ; et al.	2007-08-16
System and apparatus for using test structures inside of a chip during the fabrication of the chip Grant 7,256,055 - Aghababazadeh , et al. August 14, 2	2007-08-14
Technique for evaluating a fabrication of a die and wafer Grant 7,220,990 - Aghababazadeh , et al. May 22, 2	2007-05-22
Technique For Evaluating A Fabrication Of A Die And Wafer App 20070004063 - Aghababazadeh; Majid ; et al.	2007-01-04
System and apparatus for using test structures inside of a chip during the fabrication of the chip App 20050090027 - Aghababazadeh, Majid ; et al.	2005-04-28
Intra-chip power and test signal generation for use with test structures on wafers App 20050090916 - Aghababazadeh, Majid ; et al.	2005-04-28
Technique for evaluating a fabrication of a die and wafer App 20050085032 - Aghababazadeh, Majid ; et al.	2005-04-21
Technique for evaluating a fabrication of a semiconductor component and wafer App 20050085932 - Aghababazadeh, Majid ; et al.	2005-04-21

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