Erben; Elke

Patent Applications and Registrations

Patent applications and USPTO patent grants for Erben; Elke.The latest application filed is for "logic and flash field-effect transistors".

Company Profile

0.13.18

Erben; Elke - Dresden DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ALD process Grant 10,109,492 - Dilliway , et al. October 23, 2	2018-10-23
Logic and flash field-effect transistors Grant 10,079,242 - Richter , et al. September 18, 2	2018-09-18
Logic And Flash Field-effect Transistors App 20180158835 - Richter; Ralf ; et al.	2018-06-07
Sandwich silicidation for fully silicided gate formation Grant 9,236,440 - Boschke , et al. January 12, 2	2016-01-12
Transistor Device With Strained Layer App 20150179740 - Triyoso; Dina H. ; et al.	2015-06-25
Sandwich Silicidation For Fully Silicided Gate Formation App 20150162414 - Boschke; Roman ; et al.	2015-06-11
Method Of Forming A High Quality Interfacial Layer For A Semiconductor Device By Performing A Low Temperature Ald Process App 20140242788 - Dilliway; Gabriela ; et al.	2014-08-28
Methods for fabricating integrated circuits with fluorine passivation Grant 8,791,003 - Triyoso , et al. July 29, 2	2014-07-29
Passivating point defects in high-K gate dielectric layers during gate stack formation Grant 8,658,490 - Erben , et al. February 25, 2	2014-02-25
Methods for fabricating integrated circuits with narrow, metal filled openings Grant 8,652,890 - Schmidbauer , et al. February 18, 2	2014-02-18
Methods For Fabricating Integrated Circuits With Fluorine Passivation App 20130344692 - Triyoso; Dina ; et al.	2013-12-26
Enhanced Device Reliability Of A Semiconductor Device By Providing Superior Process Conditions In High-k Film Growth App 20130280873 - Erben; Elke ; et al.	2013-10-24
Passivating Point Defects In High-k Gate Dielectric Layers During Gate Stack Formation App 20130267086 - Erben; Elke ; et al.	2013-10-10
Methods For Fabricating Integrated Circuits With Narrow, Metal Filled Openings App 20130224927 - Schmidbauer; Sven ; et al.	2013-08-29
Methods For Fabricating Integrated Circuits With Controlled P-channel Threshold Voltage App 20130109166 - Triyoso; Dina ; et al.	2013-05-02
Methods for fabricating integrated circuits with controlled P-channel threshold voltage Grant 8,420,519 - Triyoso , et al. April 16, 2	2013-04-16
Deposition method for a transition-metal-containing dielectric Grant 7,666,752 - Kudelka , et al. February 23, 2	2010-02-23
Method of manufacturing a dielectric layer and corresponding semiconductor device Grant 7,531,405 - Spitzer , et al. May 12, 2	2009-05-12
Deposition method for a transition-metal-containing dielectric App 20080173919 - Kudelka; Stephan ; et al.	2008-07-24
Method For Forming A Dielectric Layer App 20080176375 - Erben; Elke ; et al.	2008-07-24
Method, Apparatus And Starting Material For Providing A Gaseous Precursor App 20070269598 - Kersch; Alfred ; et al.	2007-11-22
Automatic layer deposition process App 20070161180 - Erben; Elke ; et al.	2007-07-12
Method of manufacturing a dielectric layer and corresponding semiconductor device App 20060192271 - Spitzer; Andreas ; et al.	2006-08-31

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