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Patent applications and USPTO patent grants for EPIC Design Technology, Inc..The latest application filed is for "connectivity-based approach for extracting parasitic layout in an integrated circuit".
Patent | Date |
---|---|
Connectivity-based approach for extracting parasitic layout in an integrated circuit Grant 5,828,580 - Ho October 27, 1 | 1998-10-27 |
Transistor-level timing and simulator and power analyzer Grant 5,553,008 - Huang , et al. September 3, 1 | 1996-09-03 |
Transistor-level timing and power simulator and power analyzer Grant 5,446,676 - Huang , et al. August 29, 1 | 1995-08-29 |
SEC | 0000824603 | EPIC DESIGN TECHNOLOGY INC |
SEC | 0000929457 | EPIC DESIGN TECHNOLOGY INC /CA/ of CALIFORNIA |
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