Endo; Kiyotaka
Patent Applications and Registrations
Patent applications and USPTO patent grants for Endo; Kiyotaka.The latest application filed is for "semiconductor device having well contact diffusion region supplying well potential".
- Endo; Kiyotaka - Kodaira JP
- ENDO; Kiyotaka - Tokyo JP
| Patent | Date |
|---|---|
| Semiconductor Device Having Well Contact Diffusion Region Supplying Well Potential App 20220165724 - Ishimatsu; Moe ; et al. | 2022-05-26 |
| Semiconductor Device Including Pillar Transistors App 20150187935 - KOUDA; Mitsuki ; et al. | 2015-07-02 |
| Semiconductor device including pillar transistors Grant 8,994,098 - Kouda , et al. March 31, 2 | 2015-03-31 |
| Layout data creation device for creating layout data of pillar-type transistor Grant 8,847,327 - Kato , et al. September 30, 2 | 2014-09-30 |
| Semiconductor device having plural wiring layers Grant 8,686,567 - Endo , et al. April 1, 2 | 2014-04-01 |
| Semiconductor Device Including Pillar Transistors App 20140015059 - KOUDA; Mitsuki ; et al. | 2014-01-16 |
| Layout Data Creation Device For Creating Layout Data Of Pillar-type Transistor App 20130093027 - KATO; Shinji ; et al. | 2013-04-18 |
| Semiconductor Device Having Plural Wiring Layers App 20120126422 - Endo; Kiyotaka ; et al. | 2012-05-24 |
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