Emer; Joel S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Emer; Joel S..The latest application filed is for "scalable multi-die deep learning system".

Company Profile

4.44.35

Emer; Joel S. - Hudson MA
Emer; Joel S. - Acton MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Executing distributed memory operations using processing elements connected by distributed channels Grant 10,853,276 - Ahsan , et al. December 1, 2	2020-12-01
Scalable Multi-die Deep Learning System App 20200082246 - Shao; Yakun ; et al.	2020-03-12
Executing Distributed Memory Operations Using Processing Elements Connected By Distributed Channels App 20190303312 - Ahsan; Bushra ; et al.	2019-10-03
Executing distributed memory operations using processing elements connected by distributed channels Grant 10,331,583 - Ahsan , et al.	2019-06-25
High bandwidth full-block write commands Grant 10,102,124 - Steely, Jr. , et al. October 16, 2	2018-10-16
Domain state Grant 9,588,889 - Steely, Jr. , et al. March 7, 2	2017-03-07
Method and apparatus for optimizing the usage of cache memories Grant 9,418,016 - Steely, Jr. , et al. August 16, 2	2016-08-16
Signature based hit-predicting cache Grant 9,262,327 - Steely, Jr. , et al. February 16, 2	2016-02-16
Short circuit of probes in a chain Grant 9,201,792 - Steely, Jr. , et al. December 1, 2	2015-12-01
Retrieval of previously accessed data in a multi-core processor Grant 9,146,871 - Steely, Jr. , et al. September 29, 2	2015-09-29
Efficient support of sparse data structure access Grant 9,037,804 - Steely, Jr. , et al. May 19, 2	2015-05-19
Distributed Memory Operations App 20150089162 - Ahsan; Bushra ; et al.	2015-03-26
Retrieval Of Previously Accessed Data In A Multi-core Processor App 20140215162 - Steeley, JR.; Simon C. ; et al.	2014-07-31
High Bandwidth Full-block Write Commands App 20140201446 - Steeley, JR.; Simon C. ; et al.	2014-07-17
Method and apparatus for achieving non-inclusive cache performance with inclusive caches Grant 8,769,209 - Jaleel , et al. July 1, 2	2014-07-01
Domain State App 20140052920 - Steely, JR.; Simon C. ; et al.	2014-02-20
Signature Based Hit-predicting Cache App 20140006717 - STEELY, JR.; Simon C. ; et al.	2014-01-02
Short Circuit Of Probes In A Chain App 20130326147 - Steely, JR.; Simon C. ; et al.	2013-12-05
Efficient Support Of Sparse Data Structure Access App 20130297883 - Steely, JR.; Simon C. ; et al.	2013-11-07
Method And Apparatus For Achieving Non-inclusive Cache Performance With Inclusive Caches App 20120159073 - Jaleel; Aamer ; et al.	2012-06-21
Method And Apparatus For Optimizing The Usage Of Cache Memories App 20120159077 - STEELY, JR.; SIMON C. ; et al.	2012-06-21
Reconfigurable Functional Unit Having Instruction Context Storage Circuitry To Support Speculative Execution of Instructions App 20100332810 - Wang; Tao ; et al.	2010-12-30
Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system Grant 7,747,932 - Racunas , et al. June 29, 2	2010-06-29
Method and apparatus for reducing false error detection in a microprocessor Grant 7,555,703 - Mukherjee , et al. June 30, 2	2009-06-30
Method and apparatus for reducing false error detection in a redundant multi-threaded system Grant 7,543,221 - Mukherjee , et al. June 2, 2	2009-06-02
Detecting errors in directory entries Grant 7,475,321 - Gurumurthi , et al. January 6, 2	2009-01-06
Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support Grant 7,444,497 - Reinhardt , et al. October 28, 2	2008-10-28
Branch prediction combining static and dynamic prediction techniques Grant 7,404,070 - Patil , et al. July 22, 2	2008-07-22
Reducing false error detection in a microprocessor by tracking instructions neutral to errors Grant 7,386,756 - Emer , et al. June 10, 2	2008-06-10
Hardware recovery in a multi-threaded architecture Grant 7,373,548 - Reinhardt , et al. May 13, 2	2008-05-13
Implementing check instructions in each thread within a redundant multithreading environments Grant 7,353,365 - Mukherjee , et al. April 1, 2	2008-04-01
Software controlled pre-execution in a multithreaded processor Grant 7,343,602 - Luk , et al. March 11, 2	2008-03-11
Periodic checkpointing in a redundantly multi-threaded architecture Grant 7,308,607 - Reinhardt , et al. December 11, 2	2007-12-11
Incremental checkpointing in a multi-threaded architecture Grant 7,243,262 - Mukherjee , et al. July 10, 2	2007-07-10
Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system App 20070022348 - Racunas; Paul B. ; et al.	2007-01-25
Detecting errors in directory entries App 20060156155 - Gurumurthi; Sudhanva ; et al.	2006-07-13
Executing checker instructions in redundant multithreading environments App 20060095821 - Mukherjee; Shubhendu S. ; et al.	2006-05-04
Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU Grant 7,003,648 - Chrysos , et al. February 21, 2	2006-02-21
Reducing false error detection in a microprocessor by tracking instructions neutral to errors App 20050283685 - Emer, Joel S. ; et al.	2005-12-22
Method and apparatus for reducing false error detection in a microprocessor App 20050283716 - Mukherjee, Shubhendu S. ; et al.	2005-12-22
Reducing false error detection in a microprocessor by tracking dynamically dead instructions App 20050283590 - Weaver, Christopher T. ; et al.	2005-12-22
Method and apparatus for reducing false error detection in a redundant multi-threaded system App 20050283712 - Mukherjee, Shubhendu S. ; et al.	2005-12-22
Buffering unchecked stores for fault detection in redundant multithreading systems using speculative memory support App 20050193283 - Reinhardt, Steven K. ; et al.	2005-09-01
Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support App 20050154944 - Reinhardt, Steven K. ; et al.	2005-07-14
Incremental checkpointing in a multi-threaded architecture App 20050050304 - Mukherjee, Shubhendu S. ; et al.	2005-03-03
Hardware recovery in a multi-threaded architecture App 20050050386 - Reinhardt, Steven K. ; et al.	2005-03-03
Periodic checkpointing in a redundantly multi-threaded architecture App 20050050307 - Reinhardt, Steven K. ; et al.	2005-03-03
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit App 20040073905 - Emer, Joel S. ; et al.	2004-04-15
Mechanism for executing computer instructions in parallel Grant 6,704,861 - McKeen , et al. March 9, 2	2004-03-09
Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers Grant 6,675,192 - Emer , et al. January 6, 2	2004-01-06
Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU App 20030188139 - Chrysos, George Z. ; et al.	2003-10-02
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit App 20030105944 - Emer, Joel S. ; et al.	2003-06-05
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit Grant 6,493,741 - Emer , et al. December 10, 2	2002-12-10
Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information Grant 6,470,443 - Emer , et al. October 22, 2	2002-10-22
Software controlled pre-execution in a multithreaded processor App 20020055964 - Luk, Chi-Keung ; et al.	2002-05-09
Method and apparatus for employing a cycle bit parallel executing instructions Grant 6,154,828 - Macri , et al. November 28, 2	2000-11-28
Method and apparatus for predicting memory dependence using store sets Grant 6,108,770 - Chrysos , et al. August 22, 2	2000-08-22
System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction Grant 6,081,887 - Steely, Jr. , et al. June 27, 2	2000-06-27
Thread properties attribute vector based thread selection in multithreading processor Grant 6,073,159 - Emer , et al. June 6, 2	2000-06-06
Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted Grant 5,933,860 - Emer , et al. August 3, 1	1999-08-03
Method and apparatus for propagating exception conditions of a computer system Grant 5,428,807 - McKeen , et al. June 27, 1	1995-06-27
Apparatus and method for speculatively executing instructions in a computer system Grant 5,421,022 - McKeen , et al. May 30, 1	1995-05-30
Mechanism for enforcing the correct order of instruction execution Grant 5,420,990 - McKeen , et al. May 30, 1	1995-05-30
Integrated circuit chip having primary and secondary random access memories for a hierarchical cache Grant 5,285,323 - Hetherington , et al. February 8, 1	1994-02-08

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