| Patent | Date |
|---|
Single process for liner and metal fill
Grant 11,322,359 - Adusumilli , et al. May 3, 2 | 2022-05-03 |
Power decoupling attachment
Grant 11,297,717 - Shan April 5, 2 | 2022-04-05 |
Enhancement of iso-via reliability
Grant 11,227,796 - Clevenger , et al. January 18, 2 | 2022-01-18 |
Conductive contacts in semiconductor on insulator substrate
Grant 11,177,285 - Cheng , et al. November 16, 2 | 2021-11-16 |
Wimpy device by selective laser annealing
Grant 11,088,026 - Cheng , et al. August 10, 2 | 2021-08-10 |
Self-limiting fin spike removal
Grant 11,063,129 - Cheng , et al. July 13, 2 | 2021-07-13 |
Vertical transport fin field effect transistor with asymmetric channel profile
Grant 10,985,257 - Lee , et al. April 20, 2 | 2021-04-20 |
Techniques for vertical FET gate length control
Grant 10,978,576 - Liu , et al. April 13, 2 | 2021-04-13 |
Semiconductor device and method of forming the semiconductor device
Grant 10,978,454 - Anderson , et al. April 13, 2 | 2021-04-13 |
Heat pipe and vapor chamber heat dissipation
Grant 10,966,351 - Wei , et al. March 30, 2 | 2021-03-30 |
Removal of trilayer resist without damage to underlying structure
Grant 10,957,536 - Sankarapandian , et al. March 23, 2 | 2021-03-23 |
Semiconductor device with self-aligned carbon nanotube gate
Grant 10,943,786 - Cao , et al. March 9, 2 | 2021-03-09 |
Vertical transport FETs having a gradient threshold voltage
Grant 10,937,883 - Lee , et al. March 2, 2 | 2021-03-02 |
Semiconductor device with buried local interconnects
Grant 10,916,468 - Leobandung , et al. February 9, 2 | 2021-02-09 |
Dual silicide liner flow for enabling low contact resistance
Grant 10,916,471 - Adusumilli , et al. February 9, 2 | 2021-02-09 |
Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices
Grant 10,886,403 - Reznicek , et al. January 5, 2 | 2021-01-05 |
Self-forming spacers using oxidation
Grant 10,833,156 - Chan , et al. November 10, 2 | 2020-11-10 |
Methods and structures for forming uniform fins when using hardmask patterns
Grant 10,832,955 - Xu , et al. November 10, 2 | 2020-11-10 |
Simultaneously fabricating a high voltage transistor and a FinFET
Grant 10,811,410 - Cheng , et al. October 20, 2 | 2020-10-20 |
Integrated gate driver
Grant 10,804,366 - Hekmatshoartabari , et al. October 13, 2 | 2020-10-13 |
Well and punch through stopper formation using conformal doping
Grant 10,804,107 - Leobandung , et al. October 13, 2 | 2020-10-13 |
High density programmable e-fuse co-integrated with vertical FETs
Grant 10,804,278 - Balakrishnan , et al. October 13, 2 | 2020-10-13 |
Porous silicon relaxation medium for dislocation free CMOS devices
Grant 10,804,166 - Cheng , et al. October 13, 2 | 2020-10-13 |
Spacer for trench epitaxial structures
Grant 10,790,284 - Ok , et al. September 29, 2 | 2020-09-29 |
Dual channel silicon/silicon germanium complementary metal oxide semiconductor performance with interface engineering
Grant 10,790,199 - Bao , et al. September 29, 2 | 2020-09-29 |
Backside contact to a final substrate
Grant 10,790,190 - Gambino , et al. September 29, 2 | 2020-09-29 |
Package assembly for thin wafer shipping and method of use
Grant 10,784,137 - Corbin , et al. Sept | 2020-09-22 |
Gas-controlled bonding platform for edge defect reduction during wafer bonding
Grant 10,777,433 - Lin , et al. Sept | 2020-09-15 |
Fin-type FET with low source or drain contact resistance
Grant 10,777,647 - Cheng , et al. Sept | 2020-09-15 |
Multipart lid for a semiconductor package with multiple components
Grant 10,777,482 - Arvin , et al. Sept | 2020-09-15 |
Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy
Grant 10,763,343 - Reznicek , et al. Sep | 2020-09-01 |
Single Process For Liner And Metal Fill
App 20200273708 - Adusumilli; Praneet ; et al. | 2020-08-27 |
Structures, methods and applications for electrical pulse anneal processes
Grant 10,755,949 - Abou-Khalil , et al. A | 2020-08-25 |
Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
Grant 10,741,673 - Belyansky , et al. A | 2020-08-11 |
Spacer for trench epitaxial structures
Grant 10,741,559 - Ok , et al. A | 2020-08-11 |
Method of manufacturing chip-on-chip structure comprising sinterted pillars
Grant 10,734,346 - Graf , et al. | 2020-08-04 |
On-chip MIM capacitor
Grant 10,734,473 - Cheng , et al. | 2020-08-04 |
Method and structure to fabricate a nanoporous membrane
Grant 10,734,281 - Bi , et al. | 2020-08-04 |
Conductive contacts in semiconductor on insulator substrate
Grant 10,734,410 - Cheng , et al. | 2020-08-04 |
Semiconductor nanowire fabrication
Grant 10,727,051 - Borg , et al. | 2020-07-28 |
Lateral bipolar junction transistor with abrupt junction and compound buried oxide
Grant 10,727,299 - Chan , et al. | 2020-07-28 |
Three-dimensional monolithic vertical field effect transistor logic gates
Grant 10,727,139 - Hook , et al. | 2020-07-28 |
Thin film interconnects with large grains
Grant 10,727,121 - Bruce , et al. | 2020-07-28 |
Structure and method using metal spacer for insertion of variable wide line implantation in SADP/SAQP integration
Grant 10,714,389 - Chen , et al. | 2020-07-14 |
Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch
Grant 10,714,341 - Cohen , et al. | 2020-07-14 |
High aspect ratio gates
Grant 10,707,083 - Cheng , et al. | 2020-07-07 |
Techniques for creating a local interconnect using a SOI wafer
Grant 10,699,955 - Chang , et al. | 2020-06-30 |
Self-aligned low dielectric constant gate cap and a method of forming the same
Grant 10,699,951 - Pranatharthiharan , et al. | 2020-06-30 |
Method of optimizing wire RC for device performance and reliability
Grant 10,699,950 - Clevenger , et al. | 2020-06-30 |
Wrapped contacts with enhanced area
Grant 10,693,007 - Cheng , et al. | 2020-06-23 |
Single process for linear and metal fill
Grant 10,692,722 - Adusumilli , et al. | 2020-06-23 |
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