Ekbote; Shashank S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ekbote; Shashank S..The latest application filed is for "method to form silicide and contact at embedded epitaxial facet".

Company Profile

1.26.29

Ekbote; Shashank S. - Allen TX
Ekbote; Shashank S. - San Diego CA
Ekbote, Shashank S. - Richardson TX
Ekbote; Shashank S. - Irving TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method to form silicide and contact at embedded epitaxial facet Grant 10,008,499 - Lim , et al. June 26, 2	2018-06-26
Integration of analog transistor Grant 9,922,971 - Pal , et al. March 20, 2	2018-03-20
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20180047728 - LIM; Kwan-Yong ; et al.	2018-02-15
Method to form silicide and contact at embedded epitaxial facet Grant 9,812,452 - Lim , et al. November 7, 2	2017-11-07
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20170047329 - LIM; Kwan-Yong ; et al.	2017-02-16
Method to form silicide and contact at embedded epitaxial facet Grant 9,508,601 - Lim , et al. November 29, 2	2016-11-29
Integration Of Analog Transistor App 20160322352 - PAL; Himadri Sekhar ; et al.	2016-11-03
Integration of analog transistor Grant 9,412,741 - Pal , et al. August 9, 2	2016-08-09
Silicide formation due to improved SiGe faceting Grant 9,406,769 - Ekbote , et al. August 2, 2	2016-08-02
Integration Of Analog Transistor App 20160043076 - PAL; Himadri Sekhar ; et al.	2016-02-11
SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING App 20160027888 - EKBOTE; Shashank S. ; et al.	2016-01-28
Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield Grant 9,224,653 - Pal , et al. December 29, 2	2015-12-29
Integration of analog transistor Grant 9,202,810 - Pal , et al. December 1, 2	2015-12-01
Silicide formation due to improved SiGe faceting Grant 9,202,883 - Ekbote , et al. December 1, 2	2015-12-01
Silicide Formation Due To Improved Sige Faceting App 20150287801 - EKBOTE; Shashank S. ; et al.	2015-10-08
Integration Of Analog Transistor App 20150287717 - PAL; Himadri Sekhar ; et al.	2015-10-08
Integrated Circuit And Method Of Forming The Integrated Circuit With Improved Logic Transistor Performance And Sram Transistor Yield App 20150270174 - PAL; Himadri Sekhar ; et al.	2015-09-24
Native devices having improved device characteristics and methods for fabrication Grant 9,136,382 - Ekbote , et al. September 15, 2	2015-09-15
Silicide formation due to improved SiGe faceting Grant 9,093,298 - Ekbote , et al. July 28, 2	2015-07-28
Integrated circuit and method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield Grant 9,076,670 - Pal , et al. July 7, 2	2015-07-07
Method To Form Silicide And Contact At Embedded Epitaxial Facet App 20150170972 - LIM; Kwan-Yong ; et al.	2015-06-18
SILICIDE FORMATION DUE TO IMPROVED SiGe FACETING App 20150054084 - EKBOTE; Shashank S. ; et al.	2015-02-26
Integrated Circuit And Method Of Forming The Integrated Circuit With Improved Logic Transistor Performance And Sram Transistor Yield App 20150021706 - Pal; Himadri Sekhar ; et al.	2015-01-22
Integrated circuit having silicide block resistor Grant 8,748,256 - Zhao , et al. June 10, 2	2014-06-10
Native Devices Having Improved Device Characteristics And Methods For Fabrication App 20140035067 - Ekbote; Shashank S. ; et al.	2014-02-06
Native devices having improved device characteristics and methods for fabrication Grant 8,541,269 - Ekbote , et al. September 24, 2	2013-09-24
Integrated Circuit Having Silicide Block Resistor App 20130200466 - ZHAO; SONG ; et al.	2013-08-08
Low cost transistors using gate orientation and optimized implants Grant 8,405,154 - Benaissa , et al. March 26, 2	2013-03-26
Native Devices Having Improved Device Characteristics and Methods for Fabrication App 20110266635 - Ekbote; Shashank S. ; et al.	2011-11-03
Low Cost Transistors Using Gate Orientation And Optimized Implants App 20110248347 - BENAISSA; Kamel ; et al.	2011-10-13
Low cost transistors using gate orientation and optimized implants Grant 7,994,009 - Benaissa , et al. August 9, 2	2011-08-09
Method to improve transistor tox using SI recessing with no additional masking steps Grant 7,892,930 - Obradovic , et al. February 22, 2	2011-02-22
Method To Improve Transistor Tox Using Si Recessing With No Additional Masking Steps App 20110027954 - Obradovic; Borna ; et al.	2011-02-03
Low Cost Transistors Using Gate Orientation And Optimized Implants App 20100327374 - Benaissa; Kamel ; et al.	2010-12-30
Antimony ion implantation for semiconductor components Grant 7,795,122 - Bu , et al. September 14, 2	2010-09-14
Gate sidewall spacer and method of manufacture therefor Grant 7,790,561 - Rouse , et al. September 7, 2	2010-09-07
Method to improve transistor Tox using high-angle implants with no additional masks Grant 7,727,838 - Obradovic , et al. June 1, 2	2010-06-01
Semiconductor doping with improved activation Grant 7,572,716 - Bu , et al. August 11, 2	2009-08-11
Method To Improve Transistor Tox Using Si Recessing With No Additional Masking Steps App 20090093095 - Obradovic; Borna ; et al.	2009-04-09
Method Of Forming A Semiconductor Device With Source/drain Nitrogen Implant, And Related Device App 20090050980 - EKBOTE; Shashank S. ; et al.	2009-02-26
Method To Improve Transistor Tox Using High-angle Implants With No Additional Masks App 20090029516 - Obradovic; Borna ; et al.	2009-01-29
Semiconductor Doping With Improved Activation App 20080268623 - Bu; Haowen ; et al.	2008-10-30
Integration method of inversion oxide (TOXinv) thickness reduction in CMOS flow without added pattern App 20080233695 - Ekbote; Shashank S. ; et al.	2008-09-25
Method Of Fabricating Different Semiconductor Device Types With Reduced Sets Of Pattern Levels App 20070298574 - Ekbote; Shashank S. ; et al.	2007-12-27
Antimony ion implantation for semiconductor components App 20070218662 - Bu; Haowen ; et al.	2007-09-20
Novel gate sidewall spacer and method of manufacture therefor App 20070004156 - Rouse; Richard P. ; et al.	2007-01-04
Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits App 20060166457 - Liu; Sarah X. ; et al.	2006-07-27
Shallow trench isolation structure and method App 20050247994 - Mehrad, Freidoon ; et al.	2005-11-10
Shallow trench isolation structure and method Grant 6,930,018 - Mehrad , et al. August 16, 2	2005-08-16
Transistor formed from stacked disposable sidewall spacer Grant 6,706,605 - Ekbote , et al. March 16, 2	2004-03-16
Shallow trench isolation structure and method App 20040014291 - Mehrad, Freidoon ; et al.	2004-01-22