Ekbote; Shashank

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ekbote; Shashank.The latest application filed is for "three-dimensional (3d), vertically-integrated field-effect transistors (fets) for complementary metal-oxide semiconductor (cmos)".

Company Profile

2.16.17

Ekbote; Shashank - San Diego CA
Ekbote; Shashank - Allen TX
Ekbote; Shashank - Irving TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits Grant 10,861,852 - Li , et al. December 8, 2	2020-12-08
THREE-DIMENSIONAL (3D), VERTICALLY-INTEGRATED FIELD-EFFECT TRANSISTORS (FETs) FOR COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) App 20200144264 - Li; Xia ; et al.	2020-05-07
Reducing or avoiding mechanical stress in static random access memory (SRAM) strap cells Grant 10,490,558 - Choi , et al. Nov	2019-11-26
FinFET with reduced series total resistance Grant 10,304,957 - Roh , et al.	2019-05-28
Reducing Or Avoiding Mechanical Stress In Static Random Access Memory (sram) Strap Cells App 20180350819 - Choi; Youn Sung ; et al.	2018-12-06
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout Grant 10,062,768 - Choi , et al. August 28, 2	2018-08-28
Dummy gate placement methodology to enhance integrated circuit performance Grant 9,947,765 - Choi , et al. April 17, 2	2018-04-17
Finfet With Reduced Series Total Resistance App 20180076326 - Roh; Ukjin ; et al.	2018-03-15
Field-effect Transistor (fet) Devices Employing Adjacent Asymmetric Active Gate / Dummy Gate Width Layout App 20180061943 - Choi; Youn Sung ; et al.	2018-03-01
Fin field effect transistors (FETs) (FinFETs) employing dielectric material layers to apply stress to channel regions Grant 9,882,051 - Roh , et al. January 30, 2	2018-01-30
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout Grant 9,634,138 - Choi , et al. April 25, 2	2017-04-25
Dummy Gate Placement Methodology To Enhance Integrated Circuit Performance App 20170062582 - Choi; Younsung ; et al.	2017-03-02
Dummy gate placement methodology to enhance integrated circuit performance Grant 9,496,142 - Choi , et al. November 15, 2	2016-11-15
Multigate Transistor Device And Method Of Isolating Adjacent Transistors In Multigate Transistor Device Using Self-aligned Diffusion Break (sadb) App 20160093511 - SENGUPTA; Samit ; et al.	2016-03-31
Dummy Gate Placement Methodology To Enhance Integrated Circuit Performance App 20150187585 - CHOI; Younsung ; et al.	2015-07-02
Differential poly doping and circuits therefrom Grant 8,114,729 - Ekbote , et al. February 14, 2	2012-02-14
Method for forming a metal silicide Grant 7,897,513 - Bu , et al. March 1, 2	2011-03-01
MOS device and process having low resistance silicide interface using additional source/drain implant Grant 7,812,401 - Obradovic , et al. October 12, 2	2010-10-12
CD gate bias reduction and differential N+ poly doping for CMOS circuits Grant 7,718,482 - Ekbote , et al. May 18, 2	2010-05-18
Mos Device And Process Having Low Resistance Silicide Interface Using Additional Source/drain Implant App 20100109089 - OBRADOVIC; Borna ; et al.	2010-05-06
MOS device and process having low resistance silicide interface using additional source/drain implant Grant 7,682,892 - Obradovic , et al. March 23, 2	2010-03-23
Device Having Pocketless Regions and Methods of Making the Device App 20090263946 - Benaissa; Kamel ; et al.	2009-10-22
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance Grant 7,601,575 - Bu , et al. October 13, 2	2009-10-13
Differential offset spacer Grant 7,537,988 - Ekbote , et al. May 26, 2	2009-05-26
Differential Poly Doping And Circuits Therefrom App 20090096031 - EKBOTE; Shashank ; et al.	2009-04-16
Differential Offset Spacer App 20090098695 - Ekbote; Shashank ; et al.	2009-04-16
Cd Gate Bias Reduction And Differential N+ Poly Doping For Cmos Circuits App 20090098694 - Ekbote; Shashank ; et al.	2009-04-16
Mos Device And Process Having Low Resistance Silicide Interface Using Additional Source/drain Implant App 20090057759 - Obradovic; Borna ; et al.	2009-03-05
Method For Forming A Metal Silicide App 20090004853 - Bu; Haowen ; et al.	2009-01-01
Device Having Pocketless Regions and Method of Making the Device App 20080179691 - Benaissa; Kamel ; et al.	2008-07-31
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance Grant 6,930,007 - Bu , et al. August 16, 2	2005-08-16
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance App 20050164431 - Bu, Haowen ; et al.	2005-07-28
Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance App 20050059228 - Bu, Haowen ; et al.	2005-03-17

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