Eisner; Cynthia Rae

Patent Applications and Registrations

Patent applications and USPTO patent grants for Eisner; Cynthia Rae.The latest application filed is for "reducing observability of memory elements in circuits".

Company Profile

0.12.10

Eisner; Cynthia Rae - Zichron Yaacov IL
Eisner; Cynthia Rae - Zichron Ya'akov IL
Eisner; Cynthia Rae - Yaacov IL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reducing observability of memory elements in circuits Grant 8,539,403 - Arbel , et al. September 17, 2	2013-09-17
Reducing Observability Of Memory Elements In Circuits App 20130007683 - Arbel; Eli ; et al.	2013-01-03
Method for multi-cycle clock gating Grant 8,245,178 - Eisner , et al. August 14, 2	2012-08-14
Software verification using hybrid explicit and symbolic model checking Grant 8,209,667 - Eisner , et al. June 26, 2	2012-06-26
Functional verification of power gated designs by compositional reasoning Grant 8,086,972 - Eisner , et al. December 27, 2	2011-12-27
Method For Multi-cycle Clock Gating App 20110010679 - Eisner; Cynthia Rae ; et al.	2011-01-13
Over approximation of integrated circuit based clock gating logic Grant 7,853,907 - Berger , et al. December 14, 2	2010-12-14
Device, system and method for formal verification Grant 7,725,851 - Eisner , et al. May 25, 2	2010-05-25
Circuit design optimization of integrated circuit based clock gated memory elements Grant 7,676,778 - Arbel , et al. March 9, 2	2010-03-09
Functional Verification Of Power Gated Designs By Compositional Reasoning App 20100017764 - Eisner; Cynthia Rae ; et al.	2010-01-21
Method for finding multi-cycle clock gating Grant 7,594,200 - Eisner , et al. September 22, 2	2009-09-22
Device to cluster Boolean functions for clock gating Grant 7,562,325 - Arbel , et al. July 14, 2	2009-07-14
Device, System and Method for Formal Verification App 20090064064 - Eisner; Cynthia Rae ; et al.	2009-03-05
Over Approximation Of Integrated Circuit Based Clock Gating Logic App 20090044154 - Berger; Israel ; et al.	2009-02-12
Clock-gating through data independent logic Grant 7,484,187 - Eisner , et al. January 27, 2	2009-01-27
Circuit Design Optimization Of Integrated Circuit Based Clock Gated Memory Elements App 20090013289 - Arbel; Eli ; et al.	2009-01-08
Apparatus For And Method Of Estimating The Quality Of Clock Gating Solutions For Integrated Circuit Design App 20080301604 - Itskovich; Alexander ; et al.	2008-12-04
Methods to cluster boolean functions for clock gating Grant 7,458,050 - Arbel , et al. November 25, 2	2008-11-25
Software verification using hybrid explicit and symbolic model checking App 20070168988 - Eisner; Cynthia Rae ; et al.	2007-07-19
Method for multi-cycle clock gating App 20070157130 - Eisner; Cynthia Rae ; et al.	2007-07-05
Clock-gating through data independent logic App 20070130549 - Eisner; Cynthia Rae ; et al.	2007-06-07

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