Ehmann; Gregory E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ehmann; Gregory E..The latest application filed is for "data processing with circuit modeling".

Company Profile

0.10.8

Ehmann; Gregory E. - Sleepy Hollow IL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data Processing With Circuit Modeling App 20100174521 - Pontius; Timothy Allen ; et al.	2010-07-08
Parallel data communication realignment of data sent in multiple groups Grant 7,085,950 - Ehmann , et al. August 1, 2	2006-08-01
Data communication bus traffic generator arrangement Grant 7,020,807 - Ehmann , et al. March 28, 2	2006-03-28
System for bus monitoring using a reconfigurable bus monitor which is adapted to report back to CPU in response to detecting certain selected events Grant 6,931,524 - Ehmann , et al. August 16, 2	2005-08-16
Parallel data communication having multiple sync codes Grant 6,920,576 - Ehmann July 19, 2	2005-07-19
Parallel data communication having skew intolerant data groups Grant 6,839,862 - Evoy , et al. January 4, 2	2005-01-04
FIFO buffer that can read and/or write multiple and/or selectable number of data words per bus cycle Grant 6,701,390 - Ehmann March 2, 2	2004-03-02
Method and system using a common reset and a slower reset clock Grant 6,611,158 - Ehmann August 26, 2	2003-08-26
Parallel data communication realignment of data sent in multiple groups App 20030065987 - Ehmann, Gregory E. ; et al.	2003-04-03
Data communication bus traffic generator arrangement App 20030056052 - Ehmann, Gregory E. ; et al.	2003-03-20
Adaptively monitoring bus signals App 20030046522 - Ehmann, Gregory E. ; et al.	2003-03-06
Method and system using a common reset and a slower reset clock App 20030020524 - Ehmann, Gregory E.	2003-01-30
Binary data memory design with data stored in low-power sense Grant 6,507,887 - Pontius , et al. January 14, 2	2003-01-14
FIFO buffer that can read and/or write multiple and /or selectable number of data words per bus cycle App 20020188767 - Ehmann, Gregory E.	2002-12-12
Parallel data communication having multiple sync codes App 20020184549 - Ehmann, Gregory E.	2002-12-05
Parallel data communication having skew intolerant data groups App 20020184552 - Evoy, David R. ; et al.	2002-12-05
Method and apparatus for efficiently implementing complex function blocks in integrated circuit designs Grant 5,963,454 - Dockser , et al. October 5, 1	1999-10-05
GTL input receiver with hysteresis Grant 5,666,068 - Ehmann September 9, 1	1997-09-09

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