Efland; Taylor R

Patent Applications and Registrations

Patent applications and USPTO patent grants for Efland; Taylor R.The latest application filed is for "multi-component electronic system having leadframe with support-free cantilever leads".

Company Profile

0.49.26

Efland; Taylor R - Richardson TX
Efland; Taylor R. - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-component electronic system having leadframe with support-free with cantilever leads Grant 8,304,868 - Amaro , et al. November 6, 2	2012-11-06
Multi-Component Electronic System Having Leadframe with Support-Free Cantilever Leads App 20120086112 - Amaro; Michael G. ; et al.	2012-04-12
Semiconductor Package Thermal Performance Enhancement and Method App 20110024895 - Koduri; Sreenivasan K. ; et al.	2011-02-03
Semiconductor Package Thermal Performance Enhancement and Method App 20090115053 - Koduri; Sreenivasan K. ; et al.	2009-05-07
Individualized low parasitic power distribution lines deposited over active integrated circuits Grant 7,514,292 - Efland , et al. April 7, 2	2009-04-07
Robust DEMOS transistors and method for making the same Grant 7,514,329 - Pendharkar , et al. April 7, 2	2009-04-07
N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects Grant 7,268,045 - Hower , et al. September 11, 2	2007-09-11
Robust DEMOS transistors and method for making the same Grant 7,238,986 - Pendharkar , et al. July 3, 2	2007-07-03
Individualized Low Parasitic Power Distribution Lines Deposited Over Active Integrated Circuits App 20070122944 - Efland; Taylor R. ; et al.	2007-05-31
Premature breakdown in submicron device geometries Grant 7,195,965 - Lin , et al. March 27, 2	2007-03-27
Individualized low parasitic power distribution lines deposited over active integrated circuits Grant 7,135,759 - Efland , et al. November 14, 2	2006-11-14
Circuit method integrating the power distribution functions of the circuits and leadframes into the chip surface Grant 7,060,607 - Efland June 13, 2	2006-06-13
Robust DEMOS transistors and method for making the same App 20060113592 - Pendharkar; Sameer ; et al.	2006-06-01
Integrated power circuits with distributed bonding and current flow Grant 7,045,903 - Efland , et al. May 16, 2	2006-05-16
Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface Grant 6,972,484 - Efland December 6, 2	2005-12-06
N-channel LDMOS with buried P-type region to prevent parasitic bipolar effects App 20050255655 - Hower, Philip L. ; et al.	2005-11-17
Robust DEMOS transistors and method for making the same App 20050253191 - Pendharkar, Sameer ; et al.	2005-11-17
Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface App 20050248027 - Efland, Taylor R.	2005-11-10
N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects Grant 6,958,515 - Hower , et al. October 25, 2	2005-10-25
Low cost fabrication method for high voltage, high drain current MOS transistor Grant 6,930,005 - Efland , et al. August 16, 2	2005-08-16
Low leakage power transistor and method of forming Grant 6,908,859 - Pendharkar , et al. June 21, 2	2005-06-21
Low cost fabrication method for high voltage, high drain current MOS transistor App 20050118753 - Efland, Taylor R. ; et al.	2005-06-02
MOS transistors having higher drain current without reduced breakdown voltage Grant 6,873,021 - Mitros , et al. March 29, 2	2005-03-29
Line self protecting multiple output power IC architecture Grant 6,784,493 - Efland , et al. August 31, 2	2004-08-31
Thermally enhanced semiconductor chip having integrated bonds over active circuits Grant 6,784,539 - Efland August 31, 2	2004-08-31
Array of transistors with low voltage collector protection Grant 6,770,935 - Efland , et al. August 3, 2	2004-08-03
Tank-isolated-drain-extended power device Grant 6,753,575 - Efland , et al. June 22, 2	2004-06-22
Method of fabricating a drain isolated LDMOS device Grant 6,729,886 - Efland , et al. May 4, 2	2004-05-04
Premature breakdown in submicron device geometries App 20040079991 - Lin, John ; et al.	2004-04-29
Distributed power device with dual function minority carrier reduction Grant 6,710,427 - Efland , et al. March 23, 2	2004-03-23
Method of fabricating integrated system on a chip protection circuit Grant 6,709,900 - Efland , et al. March 23, 2	2004-03-23
Integrated circuit with bonding layer over active circuitry Grant 6,683,380 - Efland , et al. January 27, 2	2004-01-27
Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology Grant 6,680,226 - Efland , et al. January 20, 2	2004-01-20
Thermally enhanced semiconductor chip having integrated bonds over active circuits App 20040004282 - Efland, Taylor R.	2004-01-08
Method of fabricating a drain isolated LDMOS device App 20030228737 - Efland, Taylor R. ; et al.	2003-12-11
In line self protecting multiple output power IC architecture App 20030228729 - Efland, Taylor R. ; et al.	2003-12-11
Method of forming a distributed power device with low voltage collector protection App 20030228730 - Efland, Taylor R. ; et al.	2003-12-11
Integrated System On A Chip Protection Circuit App 20030228721 - Efland, Taylor R. ; et al.	2003-12-11
Tank-isolated-drain-extended power device App 20030228732 - Efland, Taylor R. ; et al.	2003-12-11
Method Of Building A Distributed Power Device With Dual Function Minority Carrier Reduction App 20030227070 - Efland, Taylor R. ; et al.	2003-12-11
Thermally enhanced semiconductor chip having integrated bonds over active circuits Grant 6,597,065 - Efland July 22, 2	2003-07-22
Low leakage power transistor and method of forming App 20030073313 - Pendharkar, Sameer P. ; et al.	2003-04-17
Integrated circuit with bonding layer over active circuitry App 20030036256 - Efland, Taylor R. ; et al.	2003-02-20
Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology App 20030032231 - Efland, Taylor R. ; et al.	2003-02-13
Methods and devices for optimized digital and analog CMOS transistor performance in deep submicron technology Grant 6,468,849 - Efland , et al. October 22, 2	2002-10-22
LDMOS with improved safe operating area App 20020109184 - Hower, Philip L. ; et al.	2002-08-15
LDMOS power device with oversized dwell Grant 6,424,005 - Tsai , et al. July 23, 2	2002-07-23
Individualized low parasitic power distribution lines deposited over active integrated circuits App 20020084516 - Efland, Taylor R. ; et al.	2002-07-04
Method To Partially Or Completely Suppress Pocket Implant In Selective Circuit Elements With No Additional Mask In A Cmos Flow Where Separate Masking Steps Are Used For The Drain Extension Implants For The Low Voltage And High Voltage Transistors Grant 6,413,824 - Chatterjee , et al. July 2, 2	2002-07-02
High side and low side guard rings for lowest parasitic performance in an H-bridge configuration App 20020053685 - Pendharkar, Sameer ; et al.	2002-05-09
Circuit structure integrating the power distribution functions of circuits and leadframes into the chip surface App 20020043712 - Efland, Taylor R.	2002-04-18
Method for LDMOS transistor with thick copper interconnect Grant 6,372,586 - Efland , et al. April 16, 2	2002-04-16
Integrated power circuits with distributed bonding and current flow App 20020011674 - Efland, Taylor R. ; et al.	2002-01-31
Ldmos Device With Self-aligned Resurf Region And Method Of Fabrication App 20010053581 - MOSHER, DAN M. ; et al.	2001-12-20
Integrated circuit diode, and method for fabricating same Grant 6,274,918 - Tsai , et al. August 14, 2	2001-08-14
Heat spreader Grant 6,236,098 - Efland , et al. May 22, 2	2001-05-22
Resurf LDMOS device with deep drain region Grant 6,211,552 - Efland , et al. April 3, 2	2001-04-03
Sensing of current in a synchronous-buck power stage Grant 6,160,388 - Skelton , et al. December 12, 2	2000-12-12
Plastic encapsulation for integrated circuits having plated copper top surface level interconnect Grant 6,140,702 - Efland , et al. October 31, 2	2000-10-31
Plastic encapsulation for integrated circuits having plated copper top surface level interconnect Grant 6,140,150 - Efland , et al. October 31, 2	2000-10-31
Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect Grant 6,025,275 - Efland , et al. February 15, 2	2000-02-15
Thick plated interconnect and associated auxillary interconnect Grant 6,020,640 - Efland , et al. February 1, 2	2000-02-01
Multiple transistor integrated circuit with thick copper interconnect Grant 5,859,456 - Efland , et al. January 12, 1	1999-01-12
Optimized power output clamping structure Grant 5,812,006 - Teggatz , et al. September 22, 1	1998-09-22
Method for current ballasting and busing over active device area using a multi-level conductor process Grant 5,801,091 - Efland , et al. September 1, 1	1998-09-01
CMOS power device and method of construction and layout Grant 5,744,843 - Efland , et al. April 28, 1	1998-04-28
Medium voltage LDMOS device and method of fabrication Grant 5,736,766 - Efland , et al. April 7, 1	1998-04-07
Method of making a multiple transistor integrated circuit with thick copper interconnect Grant 5,728,594 - Efland , et al. March 17, 1	1998-03-17
Device having current ballasting and busing over active area using a multi-level conductor process Grant 5,665,991 - Efland , et al. September 9, 1	1997-09-09
Windowed and segmented linear geometry source cell for power DMOS processes Grant 5,585,657 - Efland , et al. December 17, 1	1996-12-17
ESD protection structure using LDMOS diodes with thick copper interconnect Grant 5,468,984 - Efland , et al. November 21, 1	1995-11-21
Resurf lateral double diffused insulated gate field effect transistor Grant 5,406,110 - Kwon , et al. April 11, 1	1995-04-11
Lateral double diffused insulated gate field effect transistor fabrication process Grant 5,306,652 - Kwon , et al. April 26, 1	1994-04-26
Process for manufacturing a DMOS transistor Grant 5,182,222 - Malhi , et al. January 26, 1	1993-01-26
Integrated power DMOS circuit with protection diode Grant 5,119,162 - Todd , et al. June 2, 1	1992-06-02

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