Edwards; Darvin R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Edwards; Darvin R..The latest application filed is for "semiconductor package having etched foil capacitor integrated into leadframe".

Company Profile

0.21.17

Edwards; Darvin R. - Garland TX
Edwards; Darvin R - Garland TX
Edwards; Darvin R. - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor package having etched foil capacitor integrated into leadframe Grant 9,373,572 - Howard , et al. June 21, 2	2016-06-21
Semiconductor Package Having Etched Foil Capacitor Integrated Into Leadframe App 20160035655 - Howard; Gregory E. ; et al.	2016-02-04
Semiconductor package having etched foil capacitor integrated into leadframe Grant 9,165,873 - Howard , et al. October 20, 2	2015-10-20
Semiconductor package having etched foil capacitor integrated into leadframe Grant 9,142,496 - Howard , et al. September 22, 2	2015-09-22
Method for contacting agglomerate terminals of semiconductor packages Grant 8,716,068 - Edwards , et al. May 6, 2	2014-05-06
Method For Contacting Agglomerate Terminals Of Semiconductor Packages App 20140038358 - Edwards; Darvin R. ; et al.	2014-02-06
Semiconductor device having agglomerate terminals Grant 8,643,165 - Edwards , et al. February 4, 2	2014-02-04
Method For Contacting Agglomerate Terminals Of Semiconductor Packages App 20120211889 - EDWARDS; Darvin R. ; et al.	2012-08-23
Array-processed stacked semiconductor packages Grant 7,892,889 - Howard , et al. February 22, 2	2011-02-22
Array-Processed Stacked Semiconductor Packages App 20090305464 - HOWARD; Gregory E. ; et al.	2009-12-10
Array-Processed Stacked Semiconductor Packages App 20080023805 - Howard; Gregory E. ; et al.	2008-01-31
Method and apparatus to minimize power and ground bounce in a logic device Grant 7,296,168 - Edwards November 13, 2	2007-11-13
System and method for high performance heat sink for multiple chip devices Grant 7,291,913 - Edwards November 6, 2	2007-11-06
Solder joints for copper metallization having reduced interfacial voids Grant 7,267,861 - Edwards , et al. September 11, 2	2007-09-11
Temperature field controlled scheduling for processing systems Grant 7,174,194 - Chauvel , et al. February 6, 2	2007-02-06
Solder joints for copper metallization having reduced interfacial voids App 20060267157 - Edwards; Darvin R. ; et al.	2006-11-30
System and method for high performance heat sink for multiple chip devices App 20060060988 - Edwards; Darvin R.	2006-03-23
Stacked wafer scale package App 20060038272 - Edwards; Darvin R.	2006-02-23
System and method for high performance heat sink for multiple chip devices Grant 6,979,899 - Edwards December 27, 2	2005-12-27
System and method for self-leveling heat sink for multiple height devices Grant 6,950,310 - Edwards September 27, 2	2005-09-27
System and method for self-leveling heat sink for multiple height devices App 20050146023 - Edwards, Darvin R.	2005-07-07
System and method for high performance heat sink for multiple chip devices App 20050146021 - Edwards, Darvin R.	2005-07-07
System and method for delivering power to a semiconductor device App 20050133901 - Edwards, Darvin R. ; et al.	2005-06-23
Method and apparatus to minimize power and ground bounce in a logic device App 20050132243 - Edwards, Darvin R.	2005-06-16
Wafer-scale assembly of chip-size packages Grant 6,730,541 - Heinen , et al. May 4, 2	2004-05-04
Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers Grant 6,586,839 - Chisholm , et al. July 1, 2	2003-07-01
Chip-scale packages stacked on folded interconnector for vertical assembly on substrates App 20020114143 - Morrison, Gary P. ; et al.	2002-08-22
Temperature field controlled scheduling for processing systems App 20020065049 - Chauvel, Gerard ; et al.	2002-05-30
Sacrificial structures for arresting insulator cracks in semiconductor devices Grant 6,365,958 - Ibnabdeljalil , et al. April 2, 2	2002-04-02
Novel approach to structurally reinforcing the mechanical performance of silicon level interconnect layers App 20020025417 - Chisholm, Michael F. ; et al.	2002-02-28
Sacrificial Structures For Arresting Insulator Cracks In Semiconductor Devices App 20020024115 - IBNABDELJALIL, M?apos;HAMED ; et al.	2002-02-28
Wafer-scale Assemby Of Chip-size Packages App 20010044197 - HEINEN, KATHERINE G. ; et al.	2001-11-22
Method and apparatus for attaching particles to a substrate Grant 6,080,650 - Edwards June 27, 2	2000-06-27
Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board Grant 6,064,576 - Edwards , et al. May 16, 2	2000-05-16
System for modeling an integrated chip package and method of operation Grant 5,579,249 - Edwards November 26, 1	1996-11-26
Multi-chip module testing Grant 5,321,277 - Sparks , et al. June 14, 1	1994-06-14
Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof Grant 5,083,187 - Lamson , et al. January 21, 1	1992-01-21

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