Eddy; Colin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Eddy; Colin.The latest application filed is for "l1d to l2 eviction".

Company Profile

3.89.79

Eddy; Colin - Austin TX
Eddy; Colin - Round Rock TX US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
L1d To L2 Eviction App 20220171712 - Reed; Douglas Raye ; et al.	2022-06-02
Tablewalk takeover Grant 11,314,657 - Eddy April 26, 2	2022-04-26
Prefetching with level of aggressiveness based on effectiveness by memory access type Grant 10,387,318 - Hooker , et al. A	2019-08-20
Apparatus and method for programmable load replay preclusion Grant 10,228,944 - Col , et al.	2019-03-12
Apparatus and method for programmable load replay preclusion Grant 10,209,996 - Col , et al. Feb	2019-02-19
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Grant 10,175,984 - Col , et al. J	2019-01-08
Load replay precluding mechanism Grant 10,146,539 - Col , et al. De	2018-12-04
Load replay precluding mechanism Grant 10,146,546 - Col , et al. De	2018-12-04
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Grant 10,146,540 - Col , et al. De	2018-12-04
Apparatus and method to preclude non-core cache-dependent load replays in an out-of-order processor Grant 10,146,547 - Col , et al. De	2018-12-04
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor Grant 10,133,579 - Col , et al. November 20, 2	2018-11-20
Apparatus and method to preclude load replays dependent on write combining memory space access in an out-of-order processor Grant 10,133,580 - Col , et al. November 20, 2	2018-11-20
Mechanism to preclude uncacheable-dependent load replays in out-of-order processor Grant 10,127,046 - Col , et al. November 13, 2	2018-11-13
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Grant 10,120,689 - Col , et al. November 6, 2	2018-11-06
Programmable load replay precluding mechanism Grant 10,114,646 - Col , et al. October 30, 2	2018-10-30
Programmable load replay precluding mechanism Grant 10,114,794 - Col , et al. October 30, 2	2018-10-30
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Grant 10,108,428 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on long load cycles in an out-of-order processor Grant 10,108,420 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude shared RAM-dependent load replays in an out-of-order processor Grant 10,108,429 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processor Grant 10,108,430 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Grant 10,108,427 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude shared ram-dependent load replays in an out-of-order processor Grant 10,108,421 - Col , et al. October 23, 2	2018-10-23
Mechanism to preclude I/O-dependent load replays in an out-of-order processor Grant 10,095,514 - Col , et al. October 9, 2	2018-10-09
Mechanism to preclude load replays dependent on fuse array access in an out-of-order processor Grant 10,089,112 - Col , et al. October 2, 2	2018-10-02
Mechanism to preclude I/O-dependent load replays in an out-of-order processor Grant 10,088,881 - Col , et al. October 2, 2	2018-10-02
Mechanism to preclude load replays dependent on page walks in an out-of-order processor Grant 10,083,038 - Col , et al. September 25, 2	2018-09-25
Fingerprint units comparing stored static fingerprints with dynamically generated fingerprints and reconfiguring processor settings upon a fingerprint match Grant 10,019,260 - Henry , et al. July 10, 2	2018-07-10
Microprocessor with ALU integrated into store unit Grant 9,952,875 - Col , et al. April 24, 2	2018-04-24
Power saving mechanism to reduce load replays in out-of-order processor Grant 9,915,998 - Col , et al. March 13, 2	2018-03-13
Cache memory budgeted by ways based on memory access type Grant 9,910,785 - Hooker , et al. March 6, 2	2018-03-06
Processor including single invalidate page instruction Grant 9,898,418 - Eddy February 20, 2	2018-02-20
Cache memory budgeted by chunks based on memory access type Grant 9,898,411 - Hooker , et al. February 20, 2	2018-02-20
Address translation cache that supports simultaneous invalidation of common context entries Grant 9,842,055 - Eddy , et al. December 12, 2	2017-12-12
Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access type Grant 9,817,764 - Hooker , et al. November 14, 2	2017-11-14
Set associative cache memory with heterogeneous replacement policy Grant 9,811,468 - Hooker , et al. November 7, 2	2017-11-07
Cache Memory Budgeted By Ways Based On Memory Access Type App 20170315921 - HOOKER; RODNEY E. ; et al.	2017-11-02
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor Grant 9,804,845 - Col , et al. October 31, 2	2017-10-31
System And Method Of Determining Memory Ownership On Cache Line Basis For Detecting Self-modifying Code Including Modification Of A Cache Line With An Executing Instruction App 20170308477 - BEAN; BRENT ; et al.	2017-10-26
System And Method Of Determining Memory Ownership On Cache Line Basis For Detecting Self-modifying Code Including Code With Instruction That Overlaps Cache Line Boundaries App 20170308475 - BEAN; BRENT ; et al.	2017-10-26
System And Method Of Determining Memory Ownership On Cache Line Basis For Detecting Self-modifying Code Including Code With Looping Instructions App 20170308481 - BEAN; BRENT ; et al.	2017-10-26
System And Method Of Determining Memory Ownership On Cache Line Basis For Detecting Self-modifying Code App 20170308476 - BEAN; BRENT ; et al.	2017-10-26
System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructions Grant 9,798,675 - Bean , et al. October 24, 2	2017-10-24
System and method of determining memory ownership on cache line basis for detecting self-modifying code Grant 9,798,669 - Bean , et al. October 24, 2	2017-10-24
System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction Grant 9,798,670 - Bean , et al. October 24, 2	2017-10-24
Processor including load EPT instruction Grant 9,792,223 - Eddy , et al. October 17, 2	2017-10-17
System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundaries Grant 9,792,216 - Bean , et al. October 17, 2	2017-10-17
Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifier Grant 9,760,496 - Eddy September 12, 2	2017-09-12
Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processor Grant 9,740,271 - Col , et al. August 22, 2	2017-08-22
Efficient address translation caching in a processor that supports a large number of different address spaces Grant 9,727,480 - Parks , et al. August 8, 2	2017-08-08
Power saving mechanism to reduce load replays in out-of-order processor Grant 9,703,359 - Col , et al. July 11, 2	2017-07-11
Cache replacement policy that considers memory access type Grant 9,652,398 - Hooker , et al. May 16, 2	2017-05-16
Fully associative cache memory budgeted by memory access type Grant 9,652,400 - Hooker , et al. May 16, 2	2017-05-16
Mechanism to preclude load replays dependent on page walks in an out-of-order processor Grant 9,645,827 - Col , et al. May 9, 2	2017-05-09
Conditional store instructions in an out-of-order execution microprocessor Grant 9,645,822 - Henry , et al. May 9, 2	2017-05-09
Prefetching With Level Of Aggressiveness Based On Effectiveness By Memory Access Type App 20170123985 - HOOKER; RODNEY E. ; et al.	2017-05-04
Selective prefetching of physically sequential cache line to cache line that includes loaded page table entry Grant 9,569,363 - Hooker , et al. February 14, 2	2017-02-14
System and method for performing hardware prefetch tablewalks having lowest tablewalk priority Grant 9,542,332 - Eddy January 10, 2	2017-01-10
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor App 20160357568 - COL; GERARD M. ; et al.	2016-12-08
Multiple Data Prefetchers That Defer To One Another Based On Prefetch Effectiveness By Memory Access Type App 20160357677 - HOOKER; RODNEY E. ; et al.	2016-12-08
Set Associative Cache Memory With Heterogeneous Replacement Policy App 20160357680 - HOOKER; RODNEY E. ; et al.	2016-12-08
Cache Replacement Policy That Considers Memory Access Type App 20160350228 - HOOKER; RODNEY E. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor App 20160350127 - COL; Gerard M. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor App 20160350120 - COL; GERARD M. ; et al.	2016-12-01
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor App 20160349825 - COL; Gerard M. ; et al.	2016-12-01
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor App 20160350118 - COL; GERARD M. ; et al.	2016-12-01
Apparatus And Method For Programmable Load Replay Preclusion App 20160350123 - COL; GERARD M. ; et al.	2016-12-01
Load Replay Precluding Mechanism App 20160350119 - COL; GERARD M. ; et al.	2016-12-01
Cache Memory Budgeted By Chunks Based On Memory Access Type App 20160350227 - HOOKER; RODNEY E. ; et al.	2016-12-01
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor App 20160350121 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor App 20160350126 - COL; GERARD M. ; et al.	2016-12-01
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor App 20160350122 - COL; GERARD M. ; et al.	2016-12-01
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor App 20160342414 - COL; GERARD M. ; et al.	2016-11-24
Processor Including Single Invalidate Page Instruction App 20160342524 - EDDY; COLIN	2016-11-24
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor App 20160342420 - COL; GERARD M. ; et al.	2016-11-24
Microprocessor with ALU integrated into load unit Grant 9,501,286 - Col , et al. November 22, 2	2016-11-22
Processor Including Load Ept Instruction App 20160335194 - EDDY; COLIN ; et al.	2016-11-17
Cache System With A Primary Cache And An Overflow Fifo Cache App 20160259728 - EDDY; COLIN ; et al.	2016-09-08
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor App 20160209910 - COL; GERARD M. ; et al.	2016-07-21
Fully Associative Cache Memory Budgeted By Memory Access Type App 20160196214 - HOOKER; RODNEY E. ; et al.	2016-07-07
Conditional load instructions in an out-of-order execution microprocessor Grant 9,378,019 - Henry , et al. June 28, 2	2016-06-28
Simultaneous Invalidation Of All Address Translation Cache Entries Associated With X86 Process Context Identifier App 20160179688 - EDDY; COLIN	2016-06-23
Address Translation Cache That Supports Simultaneous Invalidation Of Common Context Entries App 20160179701 - EDDY; COLIN ; et al.	2016-06-23
Mechanism To Preclude Load Replays Dependent On Off-die Control Element Access In An Out-of-order Processor App 20160170761 - COL; GERARD M. ; et al.	2016-06-16
Cache System With A Primary Cache And An Overflow Cache That Use Different Indexing Schemes App 20160170884 - EDDY; COLIN ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Fuse Array Access In An Out-of-order Processor App 20160170751 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude I/o-dependent Load Replays In An Out-of-order Processor App 20160170752 - COL; GERARD M. ; et al.	2016-06-16
Programmable Load Replay Precluding Mechanism App 20160170757 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method For Programmable Load Replay Preclusion App 20160170764 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Shared Ram-dependent Load Replays In An Out-of-order Processor App 20160170759 - COL; GERARD M. ; et al.	2016-06-16
Load Replay Precluding Mechanism App 20160170754 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method To Preclude X86 Special Bus Cycle Load Replays In An Out-of-order Processor App 20160170762 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Page Walks In An Out-of-order Processor App 20160170755 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method To Preclude Load Replays Dependent On Write Combining Memory Space Access In An Out-of-order Processor App 20160170763 - COL; GERARD M. ; et al.	2016-06-16
Power Saving Mechanism To Reduce Load Replays In Out-of-order Processor App 20160170758 - COL; GERARD M. ; et al.	2016-06-16
Programmable Load Replay Precluding Mechanism App 20160170766 - COL; GERARD M. ; et al.	2016-06-16
Apparatus And Method To Preclude Non-core Cache-dependent Load Replays In An Out-of-order Processor App 20160170760 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Load Replays Dependent On Long Load Cycles In An Out-of-order Processor App 20160170756 - COL; GERARD M. ; et al.	2016-06-16
Mechanism To Preclude Uncacheable-dependent Load Replays In Out-of-order Processor App 20160170753 - COL; GERARD M. ; et al.	2016-06-16
System And Method For Performing Hardware Prefetch Tablewalks Having Lowest Tablewalk Priority App 20160140046 - Eddy; Colin	2016-05-19
Efficient Address Translation Caching In A Processor That Supports A Large Number Of Different Address Spaces App 20160041922 - PARKS; TERRY ; et al.	2016-02-11
Microprocessor that translates conditional load/store instructions into variable number of microinstructions Grant 9,244,686 - Henry , et al. January 26, 2	2016-01-26
Dynamically Reconfigurable Microprocessor App 20150089204 - Henry; G. Glenn ; et al.	2015-03-26
Microprocessor cache line evict array Grant 8,782,348 - Eddy , et al. July 15, 2	2014-07-15
Microprocessor That Translates Conditional Load/store Instructions Into Variable Number Of Microinstructions App 20140122847 - Henry; G. Glenn ; et al.	2014-05-01
Conditional Store Instructions In An Out-of-order Execution Microprocessor App 20140122843 - Henry; G. Glenn ; et al.	2014-05-01
Conditional Load Instructions In An Out-of-order Execution Microprocessor App 20140013089 - Henry; G. Glenn ; et al.	2014-01-09
Prefetching Of Next Physically Sequential Cache Line After Cache Line That Includes Loaded Page Table Entry App 20140013058 - Hooker; Rodney E. ; et al.	2014-01-09
Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications Grant 8,566,565 - Hooker , et al. October 22, 2	2013-10-22
Efficient data prefetching in the presence of load hits Grant 8,543,765 - Glover , et al. September 24, 2	2013-09-24
Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation Grant 8,539,209 - Pogor , et al. September 17, 2	2013-09-17
Guaranteed prefetch instruction Grant 8,533,437 - Henry , et al. September 10, 2	2013-09-10
Store-to-load forwarding based on load/store address computation source information comparisons Grant 8,533,438 - Hooker , et al. September 10, 2	2013-09-10
Efficient data prefetching in the presence of load hits Grant 8,489,823 - Glover , et al. July 16, 2	2013-07-16
Prefetching of next physically sequential cache line after cache line that includes loaded page table entry Grant 8,433,853 - Eddy , et al. April 30, 2	2013-04-30
Fast REP STOS using grabline operations Grant 8,392,693 - Henry , et al. March 5, 2	2013-03-05
Low power high speed load-store collision detector Grant 8,392,666 - Hooker , et al. March 5, 2	2013-03-05
Avoiding memory access latency by returning hit-modified when holding non-modified data Grant 8,364,906 - Hooker , et al. January 29, 2	2013-01-29
Efficient pseudo-LRU for colliding accesses Grant 8,301,842 - Eddy , et al. October 30, 2	2012-10-30
Efficient Data Prefetching In The Presence Of Load Hits App 20120272003 - Glover; Clinton Thomas ; et al.	2012-10-25
Efficient Data Prefetching In The Presence Of Load Hits App 20120272004 - Glover; Clinton Thomas ; et al.	2012-10-25
Multi-modal data prefetcher Grant 8,291,172 - Hooker , et al. October 16, 2	2012-10-16
Prefetching Of Next Physically Sequential Cache Line After Cache Line That Includes Loaded Page Table Entry App 20120198176 - Hooker; Rodney E. ; et al.	2012-08-02
Efficient data prefetching in the presence of load hits Grant 8,234,450 - Glover , et al. July 31, 2	2012-07-31
Prefetching of next physically sequential cache line after cache line that includes loaded page table entry Grant 8,161,246 - Hooker , et al. April 17, 2	2012-04-17
Data cache with modified bit array Grant 8,108,624 - Hooker , et al. January 31, 2	2012-01-31
Data cache with modified bit array Grant 8,108,621 - Hooker , et al. January 31, 2	2012-01-31
Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions Grant 8,069,340 - Hooker , et al. November 29, 2	2011-11-29
Multi-modal Data Prefetcher App 20110264860 - Hooker; Rodney E. ; et al.	2011-10-27
Microprocessor that performs speculative tablewalks Grant 7,996,650 - Eddy , et al. August 9, 2	2011-08-09
Avoiding Memory Access Latency By Returning Hit-modified When Holding Non-modified Data App 20110113196 - Hooker; Rodney E. ; et al.	2011-05-12
Efficient Pseudo-lru For Colliding Accesses App 20110055485 - Eddy; Colin ; et al.	2011-03-03
Fast Rep Stos Using Grabline Operations App 20110055530 - Henry; G. Glenn ; et al.	2011-03-03
Fast And Efficient Detection Of Breakpoints App 20110047314 - Pogor; Bryan Wayne ; et al.	2011-02-24
Store-to-load Forwarding Based On Load/store Address Computation Source Information Comparisons App 20110040955 - Hooker; Rodney E. ; et al.	2011-02-17
Microprocessor With Alu Integrated Into Store Unit App 20110035570 - Col; Gerard M. ; et al.	2011-02-10
Microprocessor With Alu Integrated Into Load Unit App 20110035569 - Col; Gerard M. ; et al.	2011-02-10
Efficient Data Prefetching In The Presence Of Load Hits App 20110010501 - Glover; Clinton Thomas ; et al.	2011-01-13
Guaranteed Prefetch Instruction App 20100306503 - Henry; G. Glenn ; et al.	2010-12-02
Data Cache With Modified Bit Array App 20100306475 - Hooker; Rodney E. ; et al.	2010-12-02
Data Cache With Modified Bit Array App 20100306478 - Hooker; Rodney E. ; et al.	2010-12-02
Low Power High Speed Load-store Collision Detector App 20100299484 - Hooker; Rodney E. ; et al.	2010-11-25
Microprocessor with private microcode RAM Grant 7,827,390 - Henry , et al. November 2, 2	2010-11-02
Prefetching Of Next Physically Sequential Cache Line After Cache Line That Includes Loaded Page Table Entry App 20100250859 - Hooker; Rodney E. ; et al.	2010-09-30
Microprocessor Cache Line Evict Array App 20100064107 - Eddy; Colin ; et al.	2010-03-11
Microprocessor That Performs Store Forwarding Based On Comparison Of Hashed Address Bits App 20100049952 - Eddy; Colin ; et al.	2010-02-25
Microprocessor With Multiple Operating Modes Dynamically Configurable By A Device Driver Based On Currently Running Applications App 20100011198 - Hooker; Rodney E. ; et al.	2010-01-14
Microprocessor That Performs Speculative Tablewalks App 20100011188 - Eddy; Colin ; et al.	2010-01-14
Microprocessor With Microarchitecture For Efficiently Executing Read/modify/write Memory Operand Instructions App 20090204800 - Hooker; Rodney E. ; et al.	2009-08-13
Microprocessor With Private Microcode Ram App 20080256336 - Henry; G. Glenn ; et al.	2008-10-16