Eccles; Robert E.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Eccles; Robert E..The latest application filed is for "method and apparatus for design verification with equivalency check".
- Eccles; Robert E. - San Jose CA
- Eccles; Robert E. - Santa Clara CA
| Patent | Date |
|---|---|
| Method and apparatus for design verification with equivalency check Grant 7,143,376 - Eccles November 28, 2 | 2006-11-28 |
| Method and apparatus for rule file generation Grant 7,124,382 - Eccles , et al. October 17, 2 | 2006-10-17 |
| Method and apparatus for reducing effect of jitter Grant 7,110,446 - Eccles , et al. September 19, 2 | 2006-09-19 |
| TTL compatible merged bipolar/CMOS output buffer circuits Grant 4,678,940 - Vasseghi , et al. July 7, 1 | 1987-07-07 |
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