Ebrish; Mona A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ebrish; Mona A..The latest application filed is for "dielectric retention and method of forming memory pillar".

Company Profile

10.9.8

Ebrish; Mona A. - Albany NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dielectric Retention And Method Of Forming Memory Pillar App 20210399212 - Zare; Saba ; et al.	2021-12-23
Structure and method for equal substrate to channel height between N and P fin-FETs Grant 11,043,494 - Clevenger , et al. June 22, 2	2021-06-22
Semiconductor structures of more uniform thickness Grant 11,031,250 - Ebrish , et al. June 8, 2	2021-06-08
Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions Grant 10,818,751 - Ebrish , et al. October 27, 2	2020-10-27
Nanosheet Transistor Barrier For Electrically Isolating The Substrate From The Source Or Drain Regions App 20200279913 - Ebrish; Mona A. ; et al.	2020-09-03
Semiconductor Structures Of More Uniform Thickness App 20200176263 - Ebrish; Mona A. ; et al.	2020-06-04
Structure And Method For Equal Substrate To Channel Height Between N And P Fin-fets App 20190326289 - CLEVENGER; Lawrence A. ; et al.	2019-10-24
Reducing series resistance between source and/or drain regions and a channel region Grant 10,388,789 - Ebrish , et al. A	2019-08-20
Structure and method for equal substrate to channel height between N and P fin-FETs Grant 10,381,348 - Clevenger , et al. A	2019-08-13
Reducing series resistance between source and/or drain regions and a channel region Grant 10,319,855 - Ebrish , et al.	2019-06-11
Reducing Series Resistance Between Source And/or Drain Regions And A Channel Region App 20190097049 - Ebrish; Mona A. ; et al.	2019-03-28
Reducing Series Resistance Between Source And/or Drain Regions And A Channel Region App 20190097050 - Ebrish; Mona A. ; et al.	2019-03-28
Separate N and P fin etching for reduced CMOS device leakage Grant 10,229,910 - Chu , et al.	2019-03-12
Structure And Method For Equal Substrate To Channel Height Between N And P Fin-fets App 20180197858 - CLEVENGER; Lawrence A. ; et al.	2018-07-12
Separate N And P Fin Etching For Reduced Cmos Device Leakage App 20180097002 - Chu; Isabel C. ; et al.	2018-04-05
Separate N and P fin etching for reduced CMOS device leakage Grant 9,711,507 - Chu , et al. July 18, 2	2017-07-18
Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate Grant 9,666,486 - Ebrish , et al. May 30, 2	2017-05-30

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