Eaton, Jr.; Sargent S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Eaton, Jr.; Sargent S..The latest application filed is for "method and apparatus of reducing latch-up susceptibility in cmos integrated circuits".
- Eaton, Jr.; Sargent S. - Colorado Springs CO
| Patent | Date |
|---|---|
| Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits Grant 4,571,505 - Eaton, Jr. February 18, 1 | 1986-02-18 |
| Dynamic random access memory cell with increased signal margin Grant 4,491,936 - Eaton, Jr. , et al. January 1, 1 | 1985-01-01 |
| Redundancy scheme for a dynamic RAM Grant 4,389,715 - Eaton, Jr. , et al. June 21, 1 | 1983-06-21 |
| Dummy cell arrangement for an MOS memory Grant 4,363,111 - Heightley , et al. December 7, 1 | 1982-12-07 |
| High voltage clock generator Grant 4,354,123 - Eaton, Jr. October 12, 1 | 1982-10-12 |
| Folded bit line-shared sense amplifiers Grant 4,351,034 - Eaton, Jr. , et al. September 21, 1 | 1982-09-21 |
| High speed data transfer for a semiconductor memory Grant 4,344,156 - Eaton, Jr. , et al. August 10, 1 | 1982-08-10 |
| Refresh counter Grant 4,296,480 - Eaton, Jr. , et al. October 20, 1 | 1981-10-20 |
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