eASIC Corporation

Patent Applications and Registrations

Patent applications and USPTO patent grants for eASIC Corporation.The latest application filed is for "rom segmented bitline circuit".

Company Profile

0.40.38

eASIC Corporation - Santa Clara CA
eASIC Corporation; - US
eASIC Corporation - 2001 Walsh Avenue Santa Clara CA
Easic Corporation - San Jose CA
eASIC Corp. - 3555 Woodford Drive San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
ROM segmented bitline circuit Grant 9,704,874 - Wong , et al. July 11, 2	2017-07-11
Multiple write during simultaneous memory access of a multi-port memory device Grant RE46,474 - Ngu , et al. July 11, 2	2017-07-11
Rom Segmented Bitline Circuit App 20170170186 - WONG; Ban P. ; et al.	2017-06-15
Structured Integrated Circuit Device With Multiple Configurable Via Layers App 20160293541 - ANDREEV; Alexander ; et al.	2016-10-06
Multi-chip Packaged Function Including A Programmable Device And A Fixed Function Die And Use For Application Acceleration App 20160124899 - VASISHTA; Ronnie ; et al.	2016-05-05
Architectural floorplan for a structured ASIC manufactured on a 28 NM CMOS process lithographic node or smaller Grant 9,024,657 - Andreev , et al. May 5, 2	2015-05-05
Via-configurable high-performance logic block involving transistor chains Grant 8,957,398 - Andreev , et al. February 17, 2	2015-02-17
Multiple write during simultaneous memory access of a multi-port memory device Grant 8,848,479 - Ngu , et al. September 30, 2	2014-09-30
Via-configurable high-performance logic block architecture Grant 8,735,857 - Andreev , et al. May 27, 2	2014-05-27
Architectural Floorplan for a Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node or Smaller App 20140103959 - Andreev; Alexander ; et al.	2014-04-17
Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface App 20140103985 - Andreev; Alexander ; et al.	2014-04-17
Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node App 20140105246 - Andreev; Alexander ; et al.	2014-04-17
Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC Grant 8,677,306 - Andreev , et al. March 18, 2	2014-03-18
Via-Configurable High-Performance Logic Block Involving Transistor Chains App 20140028348 - Andreev; Alexander ; et al.	2014-01-30
Clock network fishbone architecture for a structured ASIC manufactured on a 28 NM CMOS process lithographic node Grant 8,629,548 - Andreev , et al. January 14, 2	2014-01-14
Dynamic phase alignment Grant 8,504,865 - Khor , et al. August 6, 2	2013-08-06
MEMS-based switching Grant 8,436,700 - Schmit , et al. May 7, 2	2013-05-07
Programmable vias for structured ASICs Grant 8,339,844 - Schmit , et al. December 25, 2	2012-12-25
Multiple Write During Simultaneous Memory Access Of A Multi-port Memory Device App 20120243285 - Ngu; Hui H. ; et al.	2012-09-27
Via-Configurable High-Performance Logic Block Architecture App 20120161093 - Andreev; Alexander ; et al.	2012-06-28
Configurable write policy in a memory system Grant 8,040,739 - Ngu , et al. October 18, 2	2011-10-18
Mems-based Switching App 20110067982 - Schmit; Herman ; et al.	2011-03-24
Configurable Write Policy in a Memory System App 20100195419 - Ngu; Hui Hui ; et al.	2010-08-05
Programming And Circuit Topologies For Programmable Vias App 20100182044 - Schmit; Herman	2010-07-22
Single via structured IC device Grant 7,759,971 - Mark , et al. July 20, 2	2010-07-20
Programmable via modeling Grant 7,689,960 - Park , et al. March 30, 2	2010-03-30
Structured integrated circuit device Grant 7,550,996 - Or-Bach , et al. June 23, 2	2009-06-23
Single via structured IC device App 20090109765 - Mark; Shu Ern Perng ; et al.	2009-04-30
Structured integrated circuit device Grant 7,514,959 - Or-Bach , et al. April 7, 2	2009-04-07
Structured integrated circuit device Grant 7,463,062 - Or-Bach , et al. December 9, 2	2008-12-09
Dynamic Phase Alignment App 20080263381 - Khor; Choon Keat ; et al.	2008-10-23
Programmable Vias for Structured ASICs App 20080224260 - Schmit; Herman ; et al.	2008-09-18
Structured Integrated Circuit Device App 20070188188 - Or-Bach; Zvi ; et al.	2007-08-16
Customizable power and ground pins App 20070187808 - Mihelcic; Stan J. ; et al.	2007-08-16
Programmable via modeling App 20070174801 - Park; Jonathan ; et al.	2007-07-26
Integrated circuit communication techniques App 20070080709 - Or-Bach; Zvi ; et al.	2007-04-12
Structured integrated circuit device Grant 7,157,937 - Apostol , et al. January 2, 2	2007-01-02
Semiconductor device Grant 7,105,871 - Or-Bach , et al. September 12, 2	2006-09-12
Structured integrated circuit device Grant 7,098,691 - Or-Bach , et al. August 29, 2	2006-08-29
Customizable and Programmable Cell Array App 20060176075 - Or-Bach; Zvi	2006-08-10
Structured integrated circuit device App 20060164121 - Or-Bach; Zvi ; et al.	2006-07-27
Structured integrated circuit device App 20060139057 - Or-Bach; Zvi ; et al.	2006-06-29
Customizable and programmable cell array Grant 7,068,070 - Or-Bach June 27, 2	2006-06-27
Method for fabrication of semiconductor device App 20060033124 - Or-Bach; Zvi ; et al.	2006-02-16
Customizable and programmable cell array App 20060028242 - Or-Bach; Zvi	2006-02-09
Structured integrated circuit device App 20060028241 - Apostol; Adrian ; et al.	2006-02-09
Structured integrated circuit device App 20060022705 - Or-Bach; Zvi ; et al.	2006-02-02
Customizable and programmable cell array Grant 6,989,687 - Or-Bach January 24, 2	2006-01-24
Customizable and programmable cell array Grant 6,985,012 - Or-Bach January 10, 2	2006-01-10
Semiconductor device having borderless logic array and flexible I/O Grant 6,953,956 - Or-Bach , et al. October 11, 2	2005-10-11
Array of programmable cells with customized interconnections Grant 6,930,511 - Or-Bach August 16, 2	2005-08-16
Method for fabrication of semiconductor device App 20050167701 - Or-Bach, Zvi ; et al.	2005-08-04
Customizable and programmable cell array App 20050024086 - Or-Bach, Zvi	2005-02-03
Customizable and programmable cell array App 20050015699 - Or-Bach, Zvi	2005-01-20
Customizable and programmable cell array App 20050012520 - Or-Bach, Zvi	2005-01-20
Customizable and programmable cell array Grant 6,819,136 - Or-Bach November 16, 2	2004-11-16
Method for fabrication of semiconductor device App 20040161878 - Or-Bach, Zvi ; et al.	2004-08-19
Customizable and programmable cell array Grant 6,756,811 - Or-Bach June 29, 2	2004-06-29
Method for fabrication of semiconductor device App 20040119098 - Or-Bach, Zvi ; et al.	2004-06-24
Method for design and manufacture of semiconductors Grant 6,686,253 - Or-Bach February 3, 2	2004-02-03
Customizable and programmable cell array App 20030206036 - Or-Bach, Zvi	2003-11-06
Customizable and programmable cell array Grant 6,642,744 - Or-Bach , et al. November 4, 2	2003-11-04
Semiconductor device Grant 6,331,733 - Or-Bach , et al. December 18, 2	2001-12-18
Customizable and programmable cell array Grant 6,331,790 - Or-Bach , et al. December 18, 2	2001-12-18
Semiconductor device App 20010003428 - Or-Bach, Zvi	2001-06-14
Method for design and manufacture of semiconductors Grant 6,245,634 - Or-Bach June 12, 2	2001-06-12
Integrated circuits which employ look up tables to provide highly efficient logic cells and logic functionalities Grant 6,236,229 - Or-Bach May 22, 2	2001-05-22
Integrated circuit device Grant 6,194,912 - Or-Bach February 27, 2	2001-02-27

Company Registrations

NCAGE Code	5KR73	EASIC CORPORATION
CAGE Code	5KR73	EASIC CORPORATION
DUNS	124959524	EASIC CORPORATION
SEC	0001109898	eASIC Corp of DELAWARE