Duvvury; Charvaka

Patent Applications and Registrations

Patent applications and USPTO patent grants for Duvvury; Charvaka.The latest application filed is for "system and method for efficient electrostatic discharge testing and analysis".

Company Profile

1.62.33

Duvvury; Charvaka - Plano TX
Duvvury; Charvaka - Missouri City TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for efficient electrostatic discharge testing and analysis Grant 10,725,098 - Duvvury , et al.	2020-07-28
System and Method for Efficient Electrostatic Discharge Testing and Analysis App 20180100890 - Duvvury; Charvaka ; et al.	2018-04-12
ESD protection using diode-isolated gate-grounded nMOS with diode string Grant 9,269,703 - Pok , et al. February 23, 2	2016-02-23
Esd Protection Using Diode-isolated Gate-grounded Nmos With Diode String App 20140342515 - POK; Ponnarith ; et al.	2014-11-20
ESD protection using diode-isolated gate-grounded NMOS with diode string Grant 8,829,618 - Pok , et al. September 9, 2	2014-09-09
ESD protection system optimized at board level Grant 8,755,158 - Duvvury , et al. June 17, 2	2014-06-17
ESD Protection System Optimized at Board Level App 20130293992 - Duvvury; Charvaka ; et al.	2013-11-07
MOS device with substrate potential elevation for ESD protection Grant 8,530,301 - Boselli , et al. September 10, 2	2013-09-10
Esd Protection Using Diode-isolated Gate-grounded Nmos With Diode String App 20120112286 - Pok; Ponnarith ; et al.	2012-05-10
Electrostatic Discharge Protection Having Multiply Segmented Diodes In Proximity To Transistor App 20110266624 - DUVVURY; Charvaka ; et al.	2011-11-03
ESD Protection Integrated at System Level App 20110194220 - DUVVURY; Charvaka ; et al.	2011-08-11
Local Integration Of Non-linear Sheet I Integrated Circuit Packages For Esd/eos Protection App 20110075306 - Leduc; Yves ; et al.	2011-03-31
Mos Device With Substrate Potential Elevation For Esd Protection App 20110063765 - Boselli; Gianluca ; et al.	2011-03-17
In package ESD protections of IC using a thin film polymer Grant 7,872,841 - Leduc , et al. January 18, 2	2011-01-18
Methodology to guard ESD protection circuits against precharge effects Grant 7,864,494 - Hung , et al. January 4, 2	2011-01-04
MOS device with substrate potential elevation Grant 7,838,924 - Boselli , et al. November 23, 2	2010-11-23
Methodology To Guard Esd Protection Circuits Against Precharge Effects App 20100226056 - Hung; Chih-Ming ; et al.	2010-09-09
Methodology to guard ESD protection circuits against precharge effects Grant 7,746,608 - Hung , et al. June 29, 2	2010-06-29
Local ESD protection for low-capicitance applications Grant 7,667,243 - Duvvury , et al. February 23, 2	2010-02-23
Mos Comprising Substrate Potential Elevating Circuitry For Esd Protection App 20090267154 - Boselli; Gianluca ; et al.	2009-10-29
Circuit to reduce internal ESD stress on device having multiple power supply domains Grant 7,595,968 - Hung , et al. September 29, 2	2009-09-29
In Package Esd Protections Of Ic Using A Thin Film Polymer App 20080278873 - Leduc; Yves ; et al.	2008-11-13
Semiconductor dual guardring arrangement Grant 7,348,643 - Boselli , et al. March 25, 2	2008-03-25
Local ESD Protection for Low-Capicitance Applications App 20070284666 - Duvvury; Charvaka ; et al.	2007-12-13
Semiconductor dual guardring arrangement App 20070278581 - Boselli; Gianluca ; et al.	2007-12-06
Guardwall structures for ESD protection Grant 7,282,767 - Duvvury , et al. October 16, 2	2007-10-16
ESD protection for RF power amplifier circuits Grant 7,280,330 - Oguzman , et al. October 9, 2	2007-10-09
Local ESD protection for low-capacitance applications Grant 7,277,263 - Duvvury , et al. October 2, 2	2007-10-02
Circuit to reduce internal ESD stress on device having multiple power supply domains App 20070223163 - Hung; Chih-Ming ; et al.	2007-09-27
Body-biased pMOS protection against electrostatic discharge Grant 7,256,460 - Salling , et al. August 14, 2	2007-08-14
Methodology To Guard Esd Protection Circuits Against Precharge Effects App 20070103826 - Hung; Chih-Ming ; et al.	2007-05-10
Electrostatic discharge protection device including precharge reduction Grant 7,212,387 - Duvvury , et al. May 1, 2	2007-05-01
Design implementation to suppress latchup in voltage tolerant circuits Grant 7,167,350 - Salcedo-Suner , et al. January 23, 2	2007-01-23
Guardwall structures for ESD protection Grant 7,145,204 - Duvvury , et al. December 5, 2	2006-12-05
Guardwall Structures For Esd Protection App 20060231897 - Duvvury; Charvaka ; et al.	2006-10-19
Guardwall structures for ESD protection App 20060231895 - Duvvury; Charvaka ; et al.	2006-10-19
Body-biased pMOS protection against electrostatic discharge App 20060113600 - Salling; Craig T. ; et al.	2006-06-01
Electrostatic discharge protection device including precharge reduction App 20060061929 - Duvvury; Charvaka ; et al.	2006-03-23
Local ESD protection for low-capacitance applications App 20060050453 - Duvvury; Charvaka ; et al.	2006-03-09
ESD protection for RF power amplifier circuits App 20060050452 - Oguzman; Ismail H. ; et al.	2006-03-09
Electrostatic discharge testers for undistorted human-body-model and machine-model characteristics Grant 6,933,741 - Duvvury , et al. August 23, 2	2005-08-23
ESD protection of noise decoupling capacitors Grant 6,934,136 - Duvvury August 23, 2	2005-08-23
Substrate pump ESD protection for silicon-on-insulator technologies Grant 6,933,567 - Duvvury , et al. August 23, 2	2005-08-23
Electrostatic discharge testers for undistorted human-body-model and machine-model characteristics App 20050104613 - Duvvury, Charvaka ; et al.	2005-05-19
Design implementation to suppress latchup in voltage tolerant circuits App 20050104154 - Salcedo-Suner, Jorge ; et al.	2005-05-19
Efficient ESD protection with application for low capacitance I/O pads Grant 6,858,902 - Salling , et al. February 22, 2	2005-02-22
Geometry-controllable design blocks of MOS transistors for improved ESD protection Grant 6,833,568 - Duvvury , et al. December 21, 2	2004-12-21
Output buffer and I/O protection circuit for CMOS technology Grant 6,826,026 - Duvvury , et al. November 30, 2	2004-11-30
Diode-string substrate-pumped electrostatic discharge protection App 20040212936 - Salling, Craig T. ; et al.	2004-10-28
Drain-extended MOS ESD protection structure Grant 6,804,095 - Kunz , et al. October 12, 2	2004-10-12
Geometry-controllable design blocks of MOS transistors for improved ESD protection App 20040178453 - Duvvury, Charvaka ; et al.	2004-09-16
Spreading the power dissipation in MOS transistors for improved ESD protection Grant 6,781,204 - Duvvury , et al. August 24, 2	2004-08-24
Device and method of low voltage SCR protection for high voltage failsafe ESD applications Grant 6,764,892 - Kunz , et al. July 20, 2	2004-07-20
Drain-extended MOS ESD protection structure App 20040027745 - Kunz, Keith E. ; et al.	2004-02-12
Minimization and linearization of ESD parasitic capacitance in integrated circuits Grant 6,690,066 - Lin , et al. February 10, 2	2004-02-10
Efficient design of substrate triggered ESD protection circuits Grant 6,667,865 - Duvvury , et al. December 23, 2	2003-12-23
Device and method of low voltage SCR protection for high voltage failsafe ESD applications App 20030222273 - Kunz, Keith E. ; et al.	2003-12-04
Substrate pump ESD protection for silicon-on-insulator technologies App 20030213995 - Duvvury, Charvaka ; et al.	2003-11-20
ESD protection of noise decoupling capacitors App 20030202311 - Duvvury, Charvaka	2003-10-30
High voltage protection circuit for improved oxide reliability Grant 6,633,468 - Duvvury , et al. October 14, 2	2003-10-14
Drain-extended MOS ESD protection structure Grant 6,624,487 - Kunz , et al. September 23, 2	2003-09-23
Device and method of low voltage SCR protection for high voltage failsafe ESD applications Grant 6,576,959 - Kunz , et al. June 10, 2	2003-06-10
Semiconductor device with protection circuitry and method Grant 6,534,833 - Duvvury , et al. March 18, 2	2003-03-18
Output buffer and I/O protection circuit for CMOS technology App 20030048588 - Duvvury, Charvaka ; et al.	2003-03-13
Integrated circuit design error detector for electrostatic discharge and latch-up applications Grant 6,493,850 - Venugopal , et al. December 10, 2	2002-12-10
Integrated circuit design error detector for electrostatic discharge and latch-up applications App 20020152447 - Venugopal, Puvvada ; et al.	2002-10-17
Device and method of low voltage SCR protection for high voltage failsafe ESD applications App 20020145164 - Kunz, Keith E. ; et al.	2002-10-10
ESD protection circuit for advanced technologies Grant 6,462,380 - Duvvury , et al. October 8, 2	2002-10-08
High voltage trigger remote-cathode SCR Grant 6,365,940 - Duvvury , et al. April 2, 2	2002-04-02
Layout for efficient ESD design of substrate triggered ESD protection circuits App 20020030954 - Duvvury, Charvaka ; et al.	2002-03-14
Semiconductor ESD protection circuit Grant 6,249,413 - Duvvury June 19, 2	2001-06-19
Efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection Grant 6,140,683 - Duvvury , et al. October 31, 2	2000-10-31
Semiconductor ESD protection circuit Grant 6,125,021 - Duvvury , et al. September 26, 2	2000-09-26
ESD protection circuit for dual 3V/5V supply devices using single thickness gate oxides Grant 6,078,083 - Amerasekera , et al. June 20, 2	2000-06-20
Method of making an efficient NPN turn-on in a high voltage DENMOS transistor for ESD protection Grant 6,071,768 - Duvvury , et al. June 6, 2	2000-06-06
Lateral DMOS design for ESD protection Grant 6,064,249 - Duvvury , et al. May 16, 2	2000-05-16
EOS/ESD protection for high density integrated circuits Grant 6,040,968 - Duvvury , et al. March 21, 2	2000-03-21
PNP driven NMOS ESD protection circuit Grant 5,982,217 - Chen , et al. November 9, 1	1999-11-09
Semiconductor ESD protection circuit Grant 5,940,258 - Duvvury August 17, 1	1999-08-17
Power device integration for built-in ESD robustness Grant 5,903,032 - Duvvury May 11, 1	1999-05-11
Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein Grant 5,796,638 - Kang , et al. August 18, 1	1998-08-18
Method of placing source contacts for efficient ESD/EOS protection in grounded substrate MOS integrated circuit Grant 5,468,667 - Diaz , et al. November 21, 1	1995-11-21
ESD/EOS protection circuits for integrated circuits Grant 5,450,267 - Diaz , et al. September 12, 1	1995-09-12
Source contact placement for efficient ESD/EOS protection in grounded substrate MOS integrated circuit Grant 5,404,041 - Diaz , et al. April 4, 1	1995-04-04
Method for forming a silicon controlled rectifier Grant 5,369,041 - Duvvury * November 29, 1	1994-11-29
CMOS sense amplifier Grant 5,343,433 - Duvvury , et al. August 30, 1	1994-08-30
CMOS sense amplifier with N-channel sensing Grant RE34,026 - Duvvury , et al. August 11, 1	1992-08-11
CMOS sense amplifier with bit line isolation Grant 5,127,739 - Duvvury , et al. July 7, 1	1992-07-07
Efficient ESD input protection scheme Grant 4,896,243 - Chatterjee , et al. January 23, 1	1990-01-23
Output buffer with improved ESD protection Grant 4,855,620 - Duvvury , et al. August 8, 1	1989-08-08
Sense amplifier with reduced instantaneous power Grant 4,627,033 - Hyslop , et al. December 2, 1	1986-12-02
CMOS sense amplifier with N-channel sensing Grant 4,608,670 - Duvvury , et al. August 26, 1	1986-08-26
Single-ended CMOS sense amplifier Grant 4,598,389 - Duvvury , et al. July 1, 1	1986-07-01