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name:-0.06483793258667
name:-0.04803991317749
name:-0.046730041503906
Dutta; Ashim Patent Filings

Dutta; Ashim

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dutta; Ashim.The latest application filed is for "nonmetallic liner around a magnetic tunnel junction".

Company Profile
45.43.59
  • Dutta; Ashim - Menands NY
  • Dutta; Ashim - Clifton Park NY
  • Dutta; Ashim - Albany NY
  • Dutta; Ashim - Boise ID
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Nonmetallic Liner Around A Magnetic Tunnel Junction
App 20220285606 - Li; Tao ;   et al.
2022-09-08
Two-bit magnetoresistive random-access memory device architecture
Grant 11,437,083 - Dutta , et al. September 6, 2
2022-09-06
Forming Self-aligned Multi-metal Interconnects
App 20220262736 - DUTTA; Ashim ;   et al.
2022-08-18
Two-bit Magnetoresistive Random-access Memory Device Architecture
App 20220254396 - Dutta; Ashim ;   et al.
2022-08-11
Method for fabricating a semiconductor device including self-aligned top via formation at line ends
Grant 11,404,317 - Arnold , et al. August 2, 2
2022-08-02
Creating different width lines and spaces in a metal layer
Grant 11,373,880 - Penny , et al. June 28, 2
2022-06-28
Forming decoupled interconnects
Grant 11,361,987 - Dutta , et al. June 14, 2
2022-06-14
Forming self-aligned multi-metal interconnects
Grant 11,355,442 - Dutta , et al. June 7, 2
2022-06-07
Selective Patterning Of Vias With Hardmasks
App 20220165612 - Arnold; John C. ;   et al.
2022-05-26
Semiconductor structure with fully aligned vias
Grant 11,302,573 - De Silva , et al. April 12, 2
2022-04-12
Footing flare pedestal structure
Grant 11,302,639 - Yang , et al. April 12, 2
2022-04-12
Pillar-based Memory Hardmask Smoothing And Stress Reduction
App 20220109099 - Rizzolo; Michael ;   et al.
2022-04-07
Creating Different Width Lines And Spaces In A Metal Layer
App 20220093414 - Penny; Christopher J ;   et al.
2022-03-24
Selective patterning of vias with hardmasks
Grant 11,276,607 - Arnold , et al. March 15, 2
2022-03-15
Interconnect structures with selective capping layer
Grant 11,251,368 - Zhou , et al. February 15, 2
2022-02-15
E-fuse with dielectric zipping
Grant 11,239,160 - Zhou , et al. February 1, 2
2022-02-01
Placing Top Vias At Line Ends By Selective Growth Of Via Mask From Line Cut Dielectric
App 20220028784 - DUTTA; Ashim ;   et al.
2022-01-27
Fully Aligned Via for Interconnect
App 20220020688 - Xie; Ruilong ;   et al.
2022-01-20
MRAM integration with BEOL interconnect including top via
Grant 11,227,892 - Dutta , et al. January 18, 2
2022-01-18
Planar resistive random-access memory (RRAM) device with a shared top electrode
Grant 11,227,997 - Dutta , et al. January 18, 2
2022-01-18
Planar Resistive Random-access Memory (rram) Device With A Shared Top Electrode
App 20220013723 - Dutta; Ashim ;   et al.
2022-01-13
Pillar-based memory hardmask smoothing and stress reduction
Grant 11,223,008 - Rizzolo , et al. January 11, 2
2022-01-11
Inverse Tone Pillar Printing
App 20210398816 - Felix; Nelson ;   et al.
2021-12-23
Embedded MRAM device with top via
Grant 11,205,678 - Dutta , et al. December 21, 2
2021-12-21
E-Fuse with Dielectric Zipping
App 20210391256 - Zhou; Tianji ;   et al.
2021-12-16
Embedding Mram Device In Advanced Interconnects
App 20210375986 - Dutta; Ashim ;   et al.
2021-12-02
Placing top vias at line ends by selective growth of via mask from line cut dielectric
Grant 11,189,561 - Dutta , et al. November 30, 2
2021-11-30
Self-aligned top vias over metal lines formed by a damascene process
Grant 11,189,527 - Philip , et al. November 30, 2
2021-11-30
Embedded MRAM device formation with self-aligned dielectric cap
Grant 11,189,783 - Arnold , et al. November 30, 2
2021-11-30
Forming Decoupled Interconnects
App 20210358801 - Dutta; Ashim ;   et al.
2021-11-18
Embedded small via anti-fuse device
Grant 11,177,213 - Yang , et al. November 16, 2
2021-11-16
MRAM device formation with controlled ion beam etch of MTJ
Grant 11,158,786 - Dutta , et al. October 26, 2
2021-10-26
Interconnect Structures With Selective Capping Layer
App 20210328137 - Zhou; Tianji ;   et al.
2021-10-21
Self-aligned top via formation at line ends
Grant 11,152,261 - Dutta , et al. October 19, 2
2021-10-19
Embedded Memory Devices
App 20210305494 - Dutta; Ashim ;   et al.
2021-09-30
Inverse tone pillar printing method using polymer brush grafts
Grant 11,133,195 - Felix , et al. September 28, 2
2021-09-28
Self-aligned top via
Grant 11,133,260 - Liu , et al. September 28, 2
2021-09-28
Embedded Metal Contamination Removal from BEOL Wafers
App 20210296118 - Sil; Devika ;   et al.
2021-09-23
Self-aligned Top Vias Over Metal Lines Formed By A Damascene Process
App 20210296169 - Philip; Timothy Mathew ;   et al.
2021-09-23
Preserving underlying dielectric layer during MRAM device formation
Grant 11,121,173 - Dutta , et al. September 14, 2
2021-09-14
Embedded MRAM Device with Top Via
App 20210242277 - Dutta; Ashim ;   et al.
2021-08-05
Bevel metal removal using ion beam etch
Grant 11,081,643 - Dutta , et al. August 3, 2
2021-08-03
Forming barrierless contact
Grant 11,081,388 - Choi , et al. August 3, 2
2021-08-03
Embedded Small Via Anti-fuse Device
App 20210233843 - Yang; Chih-Chao ;   et al.
2021-07-29
Bevel Metal Removal Using Ion Beam Etch
App 20210226120 - Dutta; Ashim ;   et al.
2021-07-22
Footing Flare Pedestal Structure
App 20210225774 - Yang; Chih-Chao ;   et al.
2021-07-22
Self-aligned contact on a semiconductor device
Grant 11,062,946 - Dutta , et al. July 13, 2
2021-07-13
Multi-layer bottom electrode for embedded memory devices
Grant 11,043,628 - Dutta , et al. June 22, 2
2021-06-22
Pillar-based Memory Hardmask Smoothing And Stress Reduction
App 20210159394 - Rizzolo; Michael ;   et al.
2021-05-27
Self-aligned Top Via
App 20210151377 - Liu; Chi-Chun ;   et al.
2021-05-20
Embedding Magneto-resistive Random-access Memory Devices Between Metal Levels
App 20210134883 - DUTTA; Ashim ;   et al.
2021-05-06
Preserving Underlying Dielectric Layer During MRAM Device Formation
App 20210126051 - Dutta; Ashim ;   et al.
2021-04-29
Self-Aligned Top Via Formation at Line Ends
App 20210125865 - Dutta; Ashim ;   et al.
2021-04-29
Multi-layer Bottom Electrode For Embedded Memory Devices
App 20210104660 - Dutta; Ashim ;   et al.
2021-04-08
Processes For Forming Fully Aligned Vias
App 20210104432 - De Silva; Ekmini Anuja ;   et al.
2021-04-08
Controlled Ion Beam Etch of MTJ
App 20210091306 - Dutta; Ashim ;   et al.
2021-03-25
Self-aligned Top Via Formation At Line Ends
App 20210090951 - Arnold; John C. ;   et al.
2021-03-25
Embedded Mram Device Formation With Self-aligned Dielectric Cap
App 20210091301 - Arnold; John ;   et al.
2021-03-25
Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication
Grant 10,957,850 - Dutta , et al. March 23, 2
2021-03-23
Selective Patterning Of Vias With Hardmasks
App 20210082746 - Arnold; John C. ;   et al.
2021-03-18
Placing Top Vias At Line Ends By Selective Growth Of Via Mask From Line Cut Dielectric
App 20210082807 - DUTTA; Ashim ;   et al.
2021-03-18
Sacrificial Buffer Layer For Metal Removal At A Bevel Edge Of A Substrate
App 20210013400 - Dutta; Ashim ;   et al.
2021-01-14
Sacrificial buffer layer for metal removal at a bevel edge of a substrate
Grant 10,892,404 - Dutta , et al. January 12, 2
2021-01-12
Encapsulated memory pillars
Grant 10,886,462 - Dutta , et al. January 5, 2
2021-01-05
Method of forming barrier free contact for metal interconnects
Grant 10,879,107 - Dutta , et al. December 29, 2
2020-12-29
Mram Integration With Beol Interconnect Including Top Via
App 20200403032 - Dutta; Ashim ;   et al.
2020-12-24
Forming Self-aligned Multi-metal Interconnects
App 20200357748 - DUTTA; Ashim ;   et al.
2020-11-12
MRAM device formation with in-situ encapsulation
Grant 10,833,258 - Dutta , et al. November 10, 2
2020-11-10
Formation of embedded magnetic random-access memory devices with multi-level bottom electrode via contacts
Grant 10,833,257 - Dutta , et al. November 10, 2
2020-11-10
Formation Of Embedded Magnetic Random-access Memory Devices With Multi-level Bottom Electrode Via Contacts
App 20200350494 - Dutta; Ashim ;   et al.
2020-11-05
Inverse Tone Pillar Printing
App 20200350177 - Felix; Nelson ;   et al.
2020-11-05
Mram Device Formation With In-situ Encapsulation
App 20200350495 - Dutta; Ashim ;   et al.
2020-11-05
Fabrication Of Embedded Memory Devices Utilizing A Self Assembled Monolayer
App 20200328251 - DUTTA; Ashim ;   et al.
2020-10-15
Hardmask stress, grain, and structure engineering for advanced memory applications
Grant 10,796,911 - Rizzolo , et al. October 6, 2
2020-10-06
Selective Encapsulation For Metal Electrodes Of Embedded Memory Devices
App 20200274066 - DUTTA; Ashim ;   et al.
2020-08-27
EUV Pattern Transfer Using Graded Hardmask
App 20200272045 - Felix; Nelson ;   et al.
2020-08-27
Direct Extreme Ultraviolet Lithography On Hard Mask With Reverse Tone
App 20200234957 - MIGNOT; Yann ;   et al.
2020-07-23
Forming Barrierless Contact
App 20200227313 - Choi; Kisik ;   et al.
2020-07-16
Formation of embedded magnetic random-access memory devices
Grant 10,707,413 - Dutta , et al.
2020-07-07
Hardmask Stress, Grain, And Structure Engineering For Advanced Memory Applications
App 20200203164 - Rizzolo; Michael ;   et al.
2020-06-25
Lithographic alignment of a conductive line to a via
Grant 10,685,879 - Arnold , et al.
2020-06-16
Systems and methods for patterning features in tantalum nitride (TaN) layer
Grant 10,672,618 - Luong , et al.
2020-06-02
Hardmask stress, grain, and structure engineering for advanced memory applications
Grant 10,672,611 - Rizzolo , et al.
2020-06-02
Encapsulated Memory Pillars
App 20200161540 - Dutta; Ashim ;   et al.
2020-05-21
Patterning material film stack with hard mask layer configured to support selective deposition on patterned resist layer
Grant 10,656,527 - De Silva , et al.
2020-05-19
Self-aligned Contact On A Semiconductor Device
App 20200152514 - Dutta; Ashim ;   et al.
2020-05-14
Method Of Forming Barrier Free Contact For Metal Interconnects
App 20200144107 - Dutta; Ashim ;   et al.
2020-05-07
Hardmask Stress, Grain, And Structure Engineering For Advanced Memory Applications
App 20200126791 - Rizzolo; Michael ;   et al.
2020-04-23
Multi-layer Encapsulation To Enable Endpoint-based Process Control For Embedded Memory Fabrication
App 20200111951 - Dutta; Ashim ;   et al.
2020-04-09
Tone reversal during EUV pattern transfer using surface active layer assisted selective deposition
Grant 10,615,037 - Dutta , et al.
2020-04-07
Tone Reversal During Euv Pattern Transfer Using Surface Active Layer Assisted Selective Deposition
App 20200058501 - Dutta; Ashim ;   et al.
2020-02-20
Patterning Material Film Stack With Hard Mask Layer Configured To Support Selective Deposition On Patterned Resist Layer
App 20200050113 - De Silva; Ekmini Anuja ;   et al.
2020-02-13
Post-lithography defect inspection using an e-beam inspection tool
Grant 10,539,884 - Meli Thompson , et al. Ja
2020-01-21
Transferring Euv Resist Pattern To Eliminate Pattern Transfer Defectivity
App 20190348292 - Dutta; Ashim ;   et al.
2019-11-14
Post-lithography Defect Inspection Using An E-beam Inspection Tool
App 20190258171 - Meli Thompson; Luciana ;   et al.
2019-08-22
Patterning Material Film Stack With Hard Mask Layer Configured To Support Selective Deposition On Patterned Resist Layer
App 20190196340 - De Silva; Ekmini Anuja ;   et al.
2019-06-27
Systems and Methods for Patterning Features in Tantalum Nitride (TaN) Layer
App 20190096672 - Luong; Vinh ;   et al.
2019-03-28
Semiconductor constructions
Grant 9,984,977 - Dutta , et al. May 29, 2
2018-05-29
Semiconductor Constructions
App 20170263563 - Dutta; Ashim ;   et al.
2017-09-14
Semiconductor constructions
Grant 9,679,852 - Dutta , et al. June 13, 2
2017-06-13
Semiconductor Constructions
App 20160005693 - Dutta; Ashim ;   et al.
2016-01-07
Method For A Dry Exhumation Without Oxidation Of A Cell And Source Line
App 20150340611 - Akhtar; Kamran ;   et al.
2015-11-26

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