Dutta; Arijit
Patent Applications and Registrations
Patent applications and USPTO patent grants for Dutta; Arijit.The latest application filed is for "techniques for gauging performance of services".
- Dutta; Arijit - Marathahalli IN
- Dutta; Arijit - Bopodi N/A IN
- Dutta; Arijit - Pune N/A IN
- Dutta; Arijit - Bangalore IN
- Dutta; Arijit - West Bengal IN
- Dutta; Arijit - New Delhi IN
- Dutta; Arijit - Kolkata IN
| Patent | Date |
|---|---|
| Techniques for gauging performance of services Grant 9,244,804 - Walia , et al. January 26, 2 | 2016-01-26 |
| Virtual image management Grant 8,479,015 - Dutta July 2, 2 | 2013-07-02 |
| Network-aware communications Grant 8,443,044 - Dutta , et al. May 14, 2 | 2013-05-14 |
| Techniques For Gauging Performance Of Services App 20130060835 - Walia; Harpreet Singh ; et al. | 2013-03-07 |
| Techniques for gauging performance of services Grant 8,326,973 - Walia , et al. December 4, 2 | 2012-12-04 |
| Network-aware Communications App 20120290670 - Dutta; Arijit ; et al. | 2012-11-15 |
| Network-aware communications Grant 8,224,900 - Dutta , et al. July 17, 2 | 2012-07-17 |
| Controlled storage utilization Grant 8,051,141 - Dutta , et al. November 1, 2 | 2011-11-01 |
| Controlled Storage Utilization App 20110087723 - Dutta; Arijit ; et al. | 2011-04-14 |
| Network-aware Communications App 20100205251 - Dutta; Arijit ; et al. | 2010-08-12 |
| Techniques For Gauging Performance Of Services App 20100161789 - Walia; Harpreet Singh ; et al. | 2010-06-24 |
| Virtual Image Management App 20100100744 - Dutta; Arijit | 2010-04-22 |
| Method and system for incorporating via redundancy in timing analysis Grant 7,673,268 - Kashyap , et al. March 2, 2 | 2010-03-02 |
| Method and system for reducing delay noise in an integrated circuit Grant 7,360,182 - Dutta , et al. April 15, 2 | 2008-04-15 |
| Method And System For Incorporating Via Redundancy In Timing Analysis App 20070256042 - Kashyap; Madhur ; et al. | 2007-11-01 |
| Method for voltage drop analysis in integreted circuits Grant 7,240,304 - Dutta , et al. July 3, 2 | 2007-07-03 |
| Method and system for reducing delay noise in an integrated circuit App 20060294478 - Dutta; Arijit ; et al. | 2006-12-28 |
| Method for voltage drop analysis in integreted circuits App 20050257077 - Dutta, Arijit ; et al. | 2005-11-17 |
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