| Patent | Date |
|---|
Test case generation for a hardware state space
Grant 11,163,661 - Kadiyala , et al. November 2, 2 | 2021-11-02 |
List insertion in test segments with non-naturally aligned data boundaries
Grant 11,094,391 - Dusanapudi , et al. August 17, 2 | 2021-08-17 |
Method, system, and apparatus for stress testing memory translation tables
Grant 11,061,821 - Dusanapudi , et al. July 13, 2 | 2021-07-13 |
Test Case Generation For A Hardware State Space
App 20210042202 - KADIYALA; MADHUSUDAN ; et al. | 2021-02-11 |
Controlling segment layout in a stress test for a processor memory with a link stack
Grant 10,877,864 - Kapoor , et al. December 29, 2 | 2020-12-29 |
Core pairing in multicore systems
Grant 10,831,620 - Dusanapudi , et al. November 10, 2 | 2020-11-10 |
System and method for testing processor errors
Grant 10,748,637 - Wu , et al. A | 2020-08-18 |
Efficiently generating effective address translations for memory management test cases
Grant 10,713,179 - Dusanapudi , et al. | 2020-07-14 |
Controlling Segment Layout In A Stress Test For A Processor Memory With A Link Stack
App 20200201728 - Kapoor; Shakti ; et al. | 2020-06-25 |
Method, System, And Apparatus For Stress Testing Memory Translation Tables
App 20200089621 - Dusanapudi; Manoj ; et al. | 2020-03-19 |
System and Method for Testing Processor Errors
App 20200035319A1 - | 2020-01-30 |
Stress testing a processor memory with a link stack
Grant 10,540,249 - Dusanapudi , et al. Ja | 2020-01-21 |
Method, system, and apparatus for stress testing memory translation tables
Grant 10,521,355 - Dusanapudi , et al. Dec | 2019-12-31 |
Efficient testing of direct memory address translation
Grant 10,489,261 - Dusanapudi , et al. Nov | 2019-11-26 |
Replicating test case data into a cache with non-naturally aligned data boundaries
Grant 10,489,259 - Dusanapudi , et al. Nov | 2019-11-26 |
Efficient testing of direct memory address translation
Grant 10,481,991 - Dusanapudi , et al. Nov | 2019-11-19 |
List insertion in test segments with non-naturally aligned data boundaries
Grant 10,438,682 - Dusanapudi , et al. O | 2019-10-08 |
List Insertion In Test Segments With Non-naturally Aligned Data Boundaries
App 20190287639 - Dusanapudi; Manoj ; et al. | 2019-09-19 |
Efficiently Generating Effective Address Translations For Memory Management Test Cases
App 20190227945 - DUSANAPUDI; MANOJ ; et al. | 2019-07-25 |
Efficiently generating effective address translations for memory management test cases
Grant 10,346,314 - Dusanapudi , et al. July 9, 2 | 2019-07-09 |
List Insertion In Test Segments With Non-naturally Aligned Data Boundaries
App 20190198132 - Dusanapudi; Manoj ; et al. | 2019-06-27 |
Method, System, And Apparatus For Stress Testing Memory Translation Tables
App 20190188146 - Dusanapudi; Manoj ; et al. | 2019-06-20 |
Validation of correctness of interrupt triggers and delivery
Grant 10,318,456 - Dusanapudi , et al. | 2019-06-11 |
Test case generation
Grant 10,318,667 - Dusanapudi , et al. | 2019-06-11 |
Validation Of Correctness Of Interrupt Triggers And Delivery
App 20190138472 - Dusanapudi; Manoj ; et al. | 2019-05-09 |
Identifying stale entries in address translation cache
Grant 10,261,917 - Bussa , et al. | 2019-04-16 |
Stress testing a processor memory with a link stack
Grant 10,261,878 - Dusanapudi , et al. | 2019-04-16 |
Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems
Grant 10,241,880 - Dusanapudi , et al. | 2019-03-26 |
Testing speculative instruction execution with test cases placed in memory segments with non-naturally aligned data boundaries
Grant 10,223,225 - Dusanapudi , et al. | 2019-03-05 |
Efficient Testing Of Direct Memory Address Translation
App 20190050315 - Dusanapudi; Manoj ; et al. | 2019-02-14 |
Efficient Testing Of Direct Memory Address Translation
App 20190050314 - Dusanapudi; Manoj ; et al. | 2019-02-14 |
Efficient testing of direct memory address translation
Grant 10,169,185 - Dusanapudi , et al. J | 2019-01-01 |
Replicating test code and test data into a cache with non-naturally aligned data boundaries
Grant 10,169,180 - Dusanapudi , et al. J | 2019-01-01 |
Efficient testing of direct memory address translation
Grant 10,169,186 - Dusanapudi , et al. J | 2019-01-01 |
Efficient validation of transactional memory in a computer processor
Grant 10,169,181 - Bussa , et al. J | 2019-01-01 |
Stress Testing A Processor Memory With A Link Stack
App 20180267875 - Dusanapudi; Manoj ; et al. | 2018-09-20 |
Stress Testing A Processor Memory With A Link Stack
App 20180267876 - Dusanapudi; Manoj ; et al. | 2018-09-20 |
Replicating test case data into a cache and cache inhibited memory
Grant 10,055,320 - Dusanapudi , et al. August 21, 2 | 2018-08-21 |
Testing a non-core MMU
Grant 10,007,568 - Dusanapudi , et al. June 26, 2 | 2018-06-26 |
Replicating Test Case Data Into A Cache With Non-naturally Aligned Data Boundaries
App 20180157567 - Dusanapudi; Manoj ; et al. | 2018-06-07 |
Testing Speculative Instruction Execution With Test Cases Placed In Memory Segments With Non-naturally Aligned Data Boundaries
App 20180129577 - Dusanapudi; Manoj ; et al. | 2018-05-10 |
Identifying Stale Entries In Address Translation Cache
App 20180121365 - Bussa; Vinod ; et al. | 2018-05-03 |
Replicating test case data into a cache with non-naturally aligned data boundaries
Grant 9,959,183 - Dusanapudi , et al. May 1, 2 | 2018-05-01 |
Replicating test case data into a cache with non-naturally aligned data boundaries
Grant 9,959,182 - Dusanapudi , et al. May 1, 2 | 2018-05-01 |
Synchronization of hardware agents in a computer system
Grant 9,940,226 - Dusanapudi , et al. April 10, 2 | 2018-04-10 |
Testing a non-core MMU
Grant 9,921,897 - Dusanapudi , et al. March 20, 2 | 2018-03-20 |
Efficient Validation Of Transactional Memory In A Computer Processor
App 20180074926 - Bussa; Vinod ; et al. | 2018-03-15 |
Test case generation
Grant 9,910,941 - Dusanapudi , et al. March 6, 2 | 2018-03-06 |
Identifying stale entries in address translation cache
Grant 9,892,060 - Bussa , et al. February 13, 2 | 2018-02-13 |
Efficiently Generating Effective Address Translations For Memory Management Test Cases
App 20180039579 - DUSANAPUDI; MANOJ ; et al. | 2018-02-08 |
Replicating Test Case Data Into A Cache And Cache Inhibited Memory
App 20180019021 - Dusanapudi; Manoj ; et al. | 2018-01-18 |
Core Pairing In Multicore Systems
App 20170364421 - Dusanapudi; Manoj ; et al. | 2017-12-21 |
Synchronization Of Hardware Agents In A Computer System
App 20170344466 - Dusanapudi; Manoj ; et al. | 2017-11-30 |
Replicating Test Code And Test Data Into A Cache With Non-naturally Aligned Data Boundaries
App 20170329688 - Dusanapudi; Manoj ; et al. | 2017-11-16 |
Replicating Test Case Data Into A Cache With Non-naturally Aligned Data Boundaries
App 20170220442 - Dusanapudi; Manoj ; et al. | 2017-08-03 |
Efficient Validation/verification Of Coherency And Snoop Filtering Mechanisms In Computing Systems
App 20170220440 - DUSANAPUDI; Manoj ; et al. | 2017-08-03 |
Replicating Test Case Data Into A Cache With Non-naturally Aligned Data Boundaries
App 20170220438 - Dusanapudi; Manoj ; et al. | 2017-08-03 |
Identifying stale entries in address translation cache
Grant 9,720,845 - Bussa , et al. August 1, 2 | 2017-08-01 |
Testing A Non-core Mmu
App 20170192869 - DUSANAPUDI; Manoj ; et al. | 2017-07-06 |
Testing A Non-core Mmu
App 20170192829 - Dusanapudi; Manoj ; et al. | 2017-07-06 |
Identifying stale entries in address translation cache
Grant 9,697,138 - Bussa , et al. July 4, 2 | 2017-07-04 |
Test Case Generation
App 20170177455 - Dusanapudi; Manoj ; et al. | 2017-06-22 |
Test Case Generation
App 20170177765 - Dusanapudi; Manoj ; et al. | 2017-06-22 |
Identifying Stale Entries In Address Translation Cache
App 20170161192 - Bussa; Vinod ; et al. | 2017-06-08 |
Identifying Stale Entries In Address Translation Cache
App 20170161208 - Bussa; Vinod ; et al. | 2017-06-08 |
Identifying Stale Entries In Address Translation Cache
App 20170161209 - Bussa; Vinod ; et al. | 2017-06-08 |
Efficient validation/verification of coherency and snoop filtering mechanisms in computing systems
Grant 9,612,929 - Dusanapudi , et al. April 4, 2 | 2017-04-04 |
Test case generation
Grant 9,594,672 - Dusanapudi , et al. March 14, 2 | 2017-03-14 |
Identifying stale entries in address translation cache
Grant 9,594,680 - Bussa , et al. March 14, 2 | 2017-03-14 |
Replicating test case data into a cache with non-naturally aligned data boundaries
Grant 9,542,290 - Dusanapudi , et al. January 10, 2 | 2017-01-10 |
Test case generation
Grant 9,514,036 - Dusanapudi , et al. December 6, 2 | 2016-12-06 |
Efficient validation of coherency between processor cores and accelerators in computer systems
Grant 9,501,408 - Dusanapudi , et al. November 22, 2 | 2016-11-22 |
Performance measurement of hardware accelerators
Grant 9,424,159 - Dusanapudi , et al. August 23, 2 | 2016-08-23 |
Verification of dynamic logical partitioning
Grant 9,298,516 - Dusanapudi , et al. March 29, 2 | 2016-03-29 |
Detecting missing write to cache/memory operations
Grant 9,287,005 - Budhabhatti , et al. March 15, 2 | 2016-03-15 |
Verification of dynamic logical partitioning
Grant 9,286,133 - Dusanapudi , et al. March 15, 2 | 2016-03-15 |
Using a buffer to replace failed memory cells in a memory component
Grant 9,128,887 - Dusanapudi , et al. September 8, 2 | 2015-09-08 |
Detecting Missing Write To Cache/memory Operations
App 20150170764 - Budhabhatti; Bhavesh D. ; et al. | 2015-06-18 |
Memory data management
Grant 9,043,569 - Dell , et al. May 26, 2 | 2015-05-26 |
Implementing DRAM failure scenarios mitigation by using buffer techniques delaying usage of RAS features in computer systems
Grant 9,015,522 - Dell , et al. April 21, 2 | 2015-04-21 |
Performance Measurement Of Hardware Accelerators
App 20150106816 - DUSANAPUDI; MANOJ ; et al. | 2015-04-16 |
Verification Of Dynamic Logical Partitioning
App 20150095607 - Dusanapudi; Manoj ; et al. | 2015-04-02 |
Verification Of Dynamic Logical Partitioning
App 20150095608 - Dusanapudi; Manoj ; et al. | 2015-04-02 |
Memory Data Management
App 20140359241 - Dell; Timothy J. ; et al. | 2014-12-04 |
Hardware verification using acceleration platform
Grant 8,832,502 - Dusanapudi , et al. September 9, 2 | 2014-09-09 |
Implementing Dram Failure Scenarios Mitigation By Using Buffer Techniques Delaying Usage Of Ras Features In Computer Systems
App 20140157044 - Dell; Timothy J. ; et al. | 2014-06-05 |
Using A Buffer To Replace Failed Memory Cells In A Memory Component
App 20140053016 - Dusanapudi; Manoj ; et al. | 2014-02-20 |
Hardware verification using ACCELERATION platform
App 20140032966 - Dusanapudi; Manoj ; et al. | 2014-01-30 |
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode
Grant 8,127,192 - Arora , et al. February 28, 2 | 2012-02-28 |
System and method for generating fast instruction and data interrupts for processor design verification and validation
Grant 8,099,559 - Choudhury , et al. January 17, 2 | 2012-01-17 |
System and method for efficiently testing cache congruence classes during processor design verification and validation
Grant 8,019,566 - Bussa , et al. September 13, 2 | 2011-09-13 |
System and method for testing multiple processor modes for processor design verification and validation
Grant 8,006,221 - Arora , et al. August 23, 2 | 2011-08-23 |
System and method for testing a large memory area during processor design verification and validation
Grant 7,992,059 - Anvekar , et al. August 2, 2 | 2011-08-02 |
Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics
Grant 7,966,521 - Bussa , et al. June 21, 2 | 2011-06-21 |
System and method for testing SLB and TLB cells during processor design verification and validation
Grant 7,797,650 - Bag , et al. September 14, 2 | 2010-09-14 |
System and method for using resource pools and instruction pools for processor design verification and validation
Grant 7,752,499 - Choudhury , et al. July 6, 2 | 2010-07-06 |
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation
Grant 7,747,908 - Choudhury , et al. June 29, 2 | 2010-06-29 |
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation
Grant 7,739,570 - Bag , et al. June 15, 2 | 2010-06-15 |
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation
Grant 7,689,886 - Arora , et al. March 30, 2 | 2010-03-30 |
System and method for re-shuffling test case instruction orders for processor design verification and validation
Grant 7,669,083 - Arora , et al. February 23, 2 | 2010-02-23 |
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation
Grant 7,661,023 - Arora , et al. February 9, 2 | 2010-02-09 |
Light Weight And High Throughput Test Case Generation Methodology For Testing Cache/tlb Intervention And Diagnostics
App 20100011248 - Bussa; Vinod ; et al. | 2010-01-14 |
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation
Grant 7,647,539 - Bussa , et al. January 12, 2 | 2010-01-12 |
Generating a Test Case Micro Generator During Processor Design Verification and Validation
App 20090307468 - Choudhury; Shubhodeep Roy ; et al. | 2009-12-10 |
System and method for pseudo-random test pattern memory allocation for processor design verification and validation
Grant 7,584,394 - Choudhury , et al. September 1, 2 | 2009-09-01 |
System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation
App 20090070631 - Arora; Sampan ; et al. | 2009-03-12 |
System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation
App 20090070546 - Choudhury; Shubhodeep Roy ; et al. | 2009-03-12 |
System and Method for Efficiently Handling Interrupts
App 20090070570 - Choudhury; Shubhodeep Roy ; et al. | 2009-03-12 |
System and Method for Testing a Large Memory Area During Processor Design Verification and Validation
App 20090070643 - Anvekar; Divya Subbarao ; et al. | 2009-03-12 |
System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation
App 20090070768 - Choudhury; Shubhodeep Roy ; et al. | 2009-03-12 |
System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation
App 20090070632 - Bag; Sandip ; et al. | 2009-03-12 |
System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation
App 20090070629 - Arora; Sampan ; et al. | 2009-03-12 |
System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation
App 20090070532 - Bussa; Vinod ; et al. | 2009-03-12 |
System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation
App 20090024876 - Arora; Sampan ; et al. | 2009-01-22 |
System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation
App 20090024886 - Arora; Sampan ; et al. | 2009-01-22 |
System And Method For Predicting Iwarx And Stwcx Instructions In Test Pattern Generation And Simulation For Processor Design Verification/validation In Interrupt Mode
App 20090024894 - Arora; Sampan ; et al. | 2009-01-22 |
System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation
App 20090024873 - Bag; Sandip ; et al. | 2009-01-22 |
System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation
App 20090024892 - Bussa; Vinod ; et al. | 2009-01-22 |
System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation
App 20090024877 - Choudhury; Shubhodeep Roy ; et al. | 2009-01-22 |
System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation
App 20090024891 - Choudhury; Shubhodeep Roy ; et al. | 2009-01-22 |
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