Durcan; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Durcan; Mark.The latest application filed is for "trench buried bit line memory devices and methods thereof".

Company Profile

0.16.12

Durcan; Mark - Boise ID

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Retrograde well structure for a CMOS imager Grant 7,619,672 - Rhodes , et al. November 17, 2	2009-11-17
Trench buried bit line memory devices and methods thereof Grant 7,365,384 - Tran , et al. April 29, 2	2008-04-29
Trench buried bit line memory devices and methods thereof App 20070040200 - Tran; Luan C. ; et al.	2007-02-22
Trench buried bit line memory devices and methods thereof Grant 7,170,124 - Tran , et al. January 30, 2	2007-01-30
Planarization process for semiconductor substrates App 20060249723 - Doan; Trung T. ; et al.	2006-11-09
Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions Grant 6,995,059 - Lowrey , et al. February 7, 2	2006-02-07
Trench buried bit line memory devices and methods thereof App 20050078534 - Tran, Luan C. ; et al.	2005-04-14
Retrograde well structure for a CMOS imager Grant 6,858,460 - Rhodes , et al. February 22, 2	2005-02-22
Planarization process for semiconductor substrates App 20040209475 - Doan, Trung T. ; et al.	2004-10-21
Trench buried bit line memory devices and methods thereof Grant 6,806,137 - Tran , et al. October 19, 2	2004-10-19
Retrograde well structure for a CMOS imager Grant 6,787,819 - Rhodes , et al. September 7, 2	2004-09-07
Retrograde well structure for a CMOS imager App 20040150736 - Rhodes, Howard E. ; et al.	2004-08-05
Planarization process for semiconductor substrates Grant 6,743,724 - Doan , et al. June 1, 2	2004-06-01
Trench buried bit line memory devices and methods thereof App 20040094789 - Tran, Luan C. ; et al.	2004-05-20
Trench buried bit line memory devices Grant 6,734,482 - Tran , et al. May 11, 2	2004-05-11
Retrograde well structure for a CMOS imager Grant 6,686,220 - Rhodes , et al. February 3, 2	2004-02-03
Retrograde well structure for a CMOS imager App 20030180982 - Rhodes, Howard E. ; et al.	2003-09-25
Retrograde well structure for a CMOS imager App 20030173572 - Rhodes, Howard E. ; et al.	2003-09-18
Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions Grant 6,599,800 - Lowrey , et al. July 29, 2	2003-07-29
Retrograde well structure for a CMOS imager Grant 6,483,129 - Rhodes , et al. November 19, 2	2002-11-19
Retrograde well structure for a CMOS imager App 20020163020 - Rhodes, Howard E. ; et al.	2002-11-07
Retrograde well structure for a CMOS imager Grant 6,445,014 - Rhodes , et al. September 3, 2	2002-09-03
Semiconductor Processing Method Using High Pressure Liquid Media Treatment App 20020001947 - CATHEY, DAVID A. ; et al.	2002-01-03
Planarization process for semiconductor substrates Grant 6,331,488 - Doan , et al. December 18, 2	2001-12-18
Retrograde well structure for a CMOS imager App 20010050382 - Rhodes, Howard E. ; et al.	2001-12-13
Planarization process for semiconductor substrates App 20010051430 - Doan, Trung T. ; et al.	2001-12-13
Retrograde well structure for a CMOS imager Grant 6,310,366 - Rhodes , et al. October 30, 2	2001-10-30
Method of forming a circuitry isolation region within a semiconductive wafer Grant 6,100,162 - Doan , et al. August 8, 2	2000-08-08

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