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Patent applications and USPTO patent grants for Durairajan; Uma.The latest application filed is for "method and circuit for row scannable latch array".
Patent | Date |
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Method and circuit for scan dump of latch array Grant 11,443,823 - Ziaja , et al. September 13, 2 | 2022-09-13 |
Method and circuit for row scannable latch array Grant 11,443,822 - Ziaja , et al. September 13, 2 | 2022-09-13 |
Method And Circuit For Scan Dump Of Latch Array App 20220139478 - ZIAJA; Thomas A. ;   et al. | 2022-05-05 |
Method And Circuit For Row Scannable Latch Array App 20220139477 - ZIAJA; Thomas A. ;   et al. | 2022-05-05 |
Implementing robust readback capture in a programmable integrated circuit Grant 10,169,264 - Zeng , et al. J | 2019-01-01 |
Memory initialization Grant 10,108,376 - Zeng , et al. October 23, 2 | 2018-10-23 |
Configurable embedded memory system Grant 9,075,930 - Kumar , et al. July 7, 2 | 2015-07-07 |
Bimodal clock generator Grant 9,018,980 - Durairajan , et al. April 28, 2 | 2015-04-28 |
Method and apparatus for using a synchronous reset pulse to reset circuitry in multiple clock domains Grant 8,912,829 - Ogden , et al. December 16, 2 | 2014-12-16 |
Configurable Embedded Memory System App 20140133246 - Kumar; Subodh ;   et al. | 2014-05-15 |
Efficient method of replicate memory data with virtual port solution Grant 8,130,587 - Liu , et al. March 6, 2 | 2012-03-06 |
Efficient Method Of Replicate Memory Data With Virtual Port Solution App 20120051131 - Liu; Zhen ;   et al. | 2012-03-01 |
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