Dupenloup; Guy
Patent Applications and Registrations
Patent applications and USPTO patent grants for Dupenloup; Guy.The latest application filed is for "verifiable multimode multipliers".
- Dupenloup; Guy - Redwood City CA
- Dupenloup; Guy - Marly-le-Roi FR
| Patent | Date |
|---|---|
| Verifiable multimode multipliers Grant 8,336,007 - Dupenloup December 18, 2 | 2012-12-18 |
| Verifiable multimode multipliers Grant 8,095,899 - Dupenloup January 10, 2 | 2012-01-10 |
| Verifiable multimode multipliers Grant 7,506,017 - Dupenloup March 17, 2 | 2009-03-17 |
| Apparatus and method for RTL modeling of a register Grant 7,308,659 - Rangan , et al. December 11, 2 | 2007-12-11 |
| Apparatus and method for RTL based full chip modeling of a programmable logic device Grant 7,178,117 - Yu , et al. February 13, 2 | 2007-02-13 |
| Automatic synthesis script generation for synopsys design compiler Grant 6,836,877 - Dupenloup December 28, 2 | 2004-12-28 |
| Efficient top-down characterization method Grant 6,421,818 - Dupenloup , et al. July 16, 2 | 2002-07-16 |
| Method of handling macro components in circuit design synthesis Grant 6,378,123 - Dupenloup April 23, 2 | 2002-04-23 |
| RTL analysis for improved logic synthesis Grant 6,295,636 - Dupenloup September 25, 2 | 2001-09-25 |
| RTL analysis tool Grant 6,292,931 - Dupenloup September 18, 2 | 2001-09-18 |
| VDHL/Verilog expertise and gate synthesis automation system Grant 6,289,498 - Dupenloup September 11, 2 | 2001-09-11 |
| Method of accessing the generic netlist created by synopsys design compilier Grant 6,263,483 - Dupenloup July 17, 2 | 2001-07-17 |
| Buffering tree analysis in mapped design Grant 6,205,572 - Dupenloup March 20, 2 | 2001-03-20 |
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