Dun; Jowei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dun; Jowei.The latest application filed is for "power device with high aspect ratio trench contacts and submicron pitches between trenches".

Company Profile

1.11.5

Dun; Jowei - San Jose CA
Dun, Jowei - Pao Shan Hsiang TW
Dun; Jowei - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned contact for trench power MOSFET Grant 10,644,118 - Xue , et al.	2020-05-05
Power device with high aspect ratio trench contacts and submicron pitches between trenches Grant 10,424,654 - Li , et al. Sept	2019-09-24
Power Device With High Aspect Ratio Trench Contacts And Submicron Pitches Between Trenches App 20180323282 - Li; Wenjun ; et al.	2018-11-08
Power device with high aspect ratio trench contacts and submicron pitches between trenches Grant 10,020,380 - Li , et al. July 10, 2	2018-07-10
Self-aligned Contact For Trench Power Mosfet App 20170288028 - Xue; Hongyong ; et al.	2017-10-05
Self-aligned contact for trench power MOSFET Grant 9,691,863 - Xue , et al. June 27, 2	2017-06-27
Self-aligned Contact For Trench Power Mosfet App 20160300917 - Xue; Hongyong ; et al.	2016-10-13
Power Device With High Aspect Ratio Trench Contacts And Submicron Pitches Between Trenches App 20160218008 - Li; Wenjun ; et al.	2016-07-28
Low temperature process for forming intermetal gap-filling insulating layers in silicon wafer integrated circuitry App 20010030351 - Wang, Ying-Lang ; et al.	2001-10-18
Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue Grant 6,291,331 - Wang , et al. September 18, 2	2001-09-18
Three-dimensional type inductor for mixed mode radio frequency device Grant 6,291,872 - Wang , et al. September 18, 2	2001-09-18
Low temperature process for forming inter-metal gap-filling insulating layers in silicon wafer integrated circuitry Grant 6,268,274 - Wang , et al. July 31, 2	2001-07-31
Method for reducing stress and improving step-coverage of tungsten interconnects and plugs Grant 5,956,609 - Lee , et al. September 21, 1	1999-09-21
Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation Grant 5,767,578 - Chang , et al. June 16, 1	1998-06-16
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,757,081 - Chang , et al. May 26, 1	1998-05-26
Surface mount and flip chip technology for total integrated circuit isolation Grant 5,753,529 - Chang , et al. May 19, 1	1998-05-19

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