Duh; Jiann-Jeng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Duh; Jiann-Jeng.The latest application filed is for "fifo memory devices having write and read control circuits that support x4n, x2n and xn data widths during ddr and sdr modes of operation".

Company Profile

0.7.7

Duh; Jiann-Jeng - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation Grant 7,246,300 - Au , et al. July 17, 2	2007-07-17
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation Grant 7,209,983 - Au , et al. April 24, 2	2007-04-24
FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation Grant 7,158,440 - Duh , et al. January 2, 2	2007-01-02
Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration Grant 7,093,047 - Au , et al. August 15, 2	2006-08-15
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same Grant 7,076,610 - Au , et al. July 11, 2	2006-07-11
FIFO memory devices having write and read control circuits that support x4N, x2N and xN data widths during DDR and SDR modes of operation App 20050041450 - Duh, Jiann-Jeng ; et al.	2005-02-24
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation App 20050005082 - Au, Mario ; et al.	2005-01-06
Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration App 20050005069 - Au, Mario ; et al.	2005-01-06
Fifo memory devices that support all four combinations of DDR or SDR write modes with DDR or SDR read modes Grant 6,795,360 - Duh , et al. September 21, 2	2004-09-21
FIFO memory devices that support all combinations of DDR and SDR read and write modes Grant 6,778,454 - Duh , et al. August 17, 2	2004-08-17
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same App 20040047209 - Lien, Chuen-Der ; et al.	2004-03-11
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same App 20040019743 - Au, Mario ; et al.	2004-01-29
FIFO memory devices that support all combinations of DDR and SDR read and write modes App 20030206475 - Duh, Jiann-Jeng ; et al.	2003-11-06
FIFO memory devices having single data rate (SDR) and dual data rate (DDR) capability App 20030112685 - Duh, Jiann-Jeng ; et al.	2003-06-19

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