| Patent | Date |
|---|
Double exposure patterning with carbonaceous hardmask
Grant 8,293,460 - Chen , et al. October 23, 2 | 2012-10-23 |
Double Exposure Patterning With Carbonaceous Hardmask
App 20090311635 - CHEN; HUI W. ; et al. | 2009-12-17 |
Method and apparatus for characterizing features formed on a substrate
Grant 7,459,319 - Smayling , et al. December 2, 2 | 2008-12-02 |
Method And Apparatus For Characterizing Features Formed On A Substrate
App 20070145998 - Smayling; Michael C. ; et al. | 2007-06-28 |
Integrated circuit layout methods
App 20070074142 - Smayling; Michael C. ; et al. | 2007-03-29 |
Method and apparatus for characterizing features formed on a substrate
Grant 7,196,350 - Smayling , et al. March 27, 2 | 2007-03-27 |
Method and apparatus for characterizing features formed on a substrate
App 20060255825 - Smayling; Michael C. ; et al. | 2006-11-16 |
Semiconductor device and method for lowering miller capacitance for high-speed microprocessors
Grant 6,743,685 - Wu , et al. June 1, 2 | 2004-06-01 |
Channel isolation using dielectric isolation structures
Grant 6,727,558 - Duane , et al. April 27, 2 | 2004-04-27 |
Semiconductor device and method for lowering miller capacitance by modifying source/drain extensions for high speed microprocessors
Grant 6,617,219 - Duane , et al. September 9, 2 | 2003-09-09 |
Method of forming low resistance gate electrode
Grant 6,376,350 - Duane , et al. April 23, 2 | 2002-04-23 |
Mask for asymmetrical transistor formation with paired transistors
Grant 6,200,862 - Gardner , et al. March 13, 2 | 2001-03-13 |
Advanced trench isolation fabrication scheme for precision polysilicon gate control
Grant 6,077,748 - Gardner , et al. June 20, 2 | 2000-06-20 |
Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment
Grant 6,069,046 - Gardner , et al. May 30, 2 | 2000-05-30 |
Asymmetrical transistor formed from a gate conductor of unequal thickness
Grant 6,040,220 - Gardner , et al. March 21, 2 | 2000-03-21 |
Air gap spacer formation for high performance MOSFETs
Grant 5,959,337 - Gardner , et al. September 28, 1 | 1999-09-28 |
Semiconductor fabrication employing a transistor gate coupled to a localized substrate
Grant 5,943,562 - Gardner , et al. August 24, 1 | 1999-08-24 |
Method of forming air gap spacer for high performance MOSFETS'
Grant 5,869,379 - Gardner , et al. February 9, 1 | 1999-02-09 |
Method for enhancing field oxide thickness at field oxide perimeters
Grant 5,686,346 - Duane November 11, 1 | 1997-11-11 |
Method for fabrication of a non-symmetrical transistor
Grant 5,672,531 - Gardner , et al. September 30, 1 | 1997-09-30 |
Method of fabricating an insulated gate field effect transistor having lightly-doped source and drain extensions using an oxide sidewall spacer method
Grant 5,145,798 - Smayling , et al. September 8, 1 | 1992-09-08 |
High density CMOS integrated circuit manufacturing process
Grant 4,677,739 - Doering , et al. July 7, 1 | 1987-07-07 |
Method of making insulated gate field effect transistor with a lightly doped drain using oxide sidewall spacer and double implantations
Grant 4,566,175 - Smayling , et al. January 28, 1 | 1986-01-28 |
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