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name:-0.012722969055176
name:-0.0013680458068848
Drizlikh; Sergei Patent Filings

Drizlikh; Sergei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Drizlikh; Sergei.The latest application filed is for "system and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process".

Company Profile
0.12.2
  • Drizlikh; Sergei - Cedar Park TX
  • Drizlikh; Sergei - Scarborough ME US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods of forming titanium-aluminum layers for gate electrodes and related semiconductor devices
Grant 9,418,856 - Bordelon , et al. August 16, 2
2016-08-16
System and method for monitoring chloride content and concentration induced by a metal etch process
Grant 8,481,142 - Budri , et al. July 9, 2
2013-07-09
Method and apparatus for reducing plasma process induced damage in integrated circuits
Grant 8,471,369 - McCulloh , et al. June 25, 2
2013-06-25
System And Method For Manufacturing An Integrated Circuit Anti-fuse In Conjunction With A Tungsten Plug Process
App 20110221031 - Drizlikh; Sergei ;   et al.
2011-09-15
System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process
Grant 7,915,093 - Drizlikh , et al. March 29, 2
2011-03-29
MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation
Grant 7,645,657 - Brisbin , et al. January 12, 2
2010-01-12
MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradation
App 20090146192 - Brisbin; Douglas ;   et al.
2009-06-11
Semiconductor device having a minimal via resistance created by applying a nitrogen plasma to a titanium via liner
Grant 7,531,896 - Drizlikh , et al. May 12, 2
2009-05-12
System and method for providing contact etch selectivity using RIE lag dependence on contact aspect ratio
Grant 7,504,340 - Drizlikh , et al. March 17, 2
2009-03-17
High Q inductor integration
Grant 7,247,544 - Drizlikh , et al. July 24, 2
2007-07-24
System and method for manufacturing an out of plane integrated circuit inductor
Grant 7,229,908 - Drizlikh , et al. June 12, 2
2007-06-12
System and method for minimizing increases in via resistance by applying a nitrogen plasma after a titanium liner deposition
Grant 7,101,787 - Drizlikh , et al. September 5, 2
2006-09-05

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