Dreps; Daniel Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dreps; Daniel Mark.The latest application filed is for "system interconnect dynamic scaling handshake using spare bit-lane".

Company Profile

0.45.33

Dreps; Daniel Mark - Austin TX
Dreps; Daniel Mark - Georgetown TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System interconnect dynamic scaling handshake using spare bit-lane Grant 9,558,139 - Dreps , et al. January 31, 2	2017-01-31
System interconnect dynamic scaling handshake using spare bit-lane Grant 9,552,319 - Dreps , et al. January 24, 2	2017-01-24
System interconnect dynamic scaling by lane width and operating frequency balancing Grant 9,529,406 - Dreps , et al. December 27, 2	2016-12-27
System interconnect dynamic scaling by lane width and operating frequency balancing Grant 9,524,013 - Dreps , et al. December 20, 2	2016-12-20
Bus interface optimization by selecting bit-lanes having best performance margins Grant 9,459,982 - Dreps , et al. October 4, 2	2016-10-04
System interconnect dynamic scaling by predicting I/O requirements Grant 9,324,031 - Dreps , et al. April 26, 2	2016-04-26
System interconnect dynamic scaling by predicting I/O requirements Grant 9,324,030 - Dreps , et al. April 26, 2	2016-04-26
System Interconnect Dynamic Scaling Handshake Using Spare Bit-lane App 20160050301 - Dreps; Daniel Mark ; et al.	2016-02-18
System Interconnect Dynamic Scaling Handshake Using Spare Bit-lane App 20160048473 - Dreps; Daniel Mark ; et al.	2016-02-18
Bus interface optimization by selecting bit-lanes having best performance margins Grant 9,244,799 - Dreps , et al. January 26, 2	2016-01-26
System Interconnect Dynamic Scaling By Lane Width And Operating Frequency Balancing App 20150301576 - Dreps; Daniel Mark ; et al.	2015-10-22
System Interconnect Dynamic Scaling By Lane Width And Operating Frequency Balancing App 20150301575 - Dreps; Daniel Mark ; et al.	2015-10-22
System Interconnect Dynamic Scaling By Predicting I/o Requirements App 20150193690 - Dreps; Daniel Mark ; et al.	2015-07-09
System Interconnect Dynamic Scaling By Predicting I/o Requirements App 20150192981 - Dreps; Daniel Mark ; et al.	2015-07-09
Bus Interface Optimization By Selecting Bit-lanes Having Best Performance Margins App 20150193316 - Dreps; Daniel Mark ; et al.	2015-07-09
Bus Interface Optimization By Selecting Bit-lanes Having Best Performance Margins App 20150193287 - Dreps; Daniel Mark ; et al.	2015-07-09
Variable voltage CMOS off-chip driver and receiver circuits Grant 8,604,828 - Bickford , et al. December 10, 2	2013-12-10
Architecture for a physical interface of a high speed front side bus Grant 7,945,805 - Baumgartner , et al. May 17, 2	2011-05-17
Self-Healing Chip-to-Chip Interface App 20110010482 - Becker; Wiren Dale ; et al.	2011-01-13
Self-healing chip-to-chip interface Grant 7,813,266 - Becker , et al. October 12, 2	2010-10-12
Programmable diagnostic memory module Grant 7,739,562 - Cases , et al. June 15, 2	2010-06-15
Implementing phase rotator circuits with embedded polyphase filter network stage Grant 7,733,984 - Baumgartner , et al. June 8, 2	2010-06-08
Method for performing memory diagnostics using a programmable diagnostic memory module Grant 7,730,369 - Cases , et al. June 1, 2	2010-06-01
Self-Healing Chip-to-Chip Interface App 20100085872 - Becker; Wiren Dale ; et al.	2010-04-08
Architecture for a physical interface of a high speed front side bus Grant 7,624,297 - Baumgartner , et al. November 24, 2	2009-11-24
Programmable Diagnostic Memory Module App 20090049339 - Cases; Moises ; et al.	2009-02-19
Method for Performing Memory Diagnostics Using a Programmable Diagnostic Memory Module App 20090049341 - Cases; Moises ; et al.	2009-02-19
System for reducing cross-talk induced source synchronous bus clock jitter Grant 7,477,068 - Truong , et al. January 13, 2	2009-01-13
System For Reducing Cross-talk Induced Source Synchronous Bus Clock Jitter App 20080175327 - Truong; Bao G. ; et al.	2008-07-24
Architecture for a Physical Interface of a High Speed Front Side Bus App 20080148088 - Baumgartner; Steven John ; et al.	2008-06-19
Architecture for a Physical Interface of a High Speed Front Side Bus App 20080147952 - Baumgartner; Steven John ; et al.	2008-06-19
Method For Reducing Cross-talk Induced Source Synchronous Bus Clock Jitter App 20080143375 - Truong; Bao G. ; et al.	2008-06-19
Digitally tunable high-current current reference with high PSRR Grant 7,385,437 - Dreps , et al. June 10, 2	2008-06-10
Method for reducing cross-talk induced source synchronous bus clock jitter Grant 7,382,151 - Truong , et al. June 3, 2	2008-06-03
Method for Implementing Phase Rotator Circuits and Phase Rotator Circuit With Embedded Polyphase Filter Network Stage App 20080107212 - Baumgartner; Steven John ; et al.	2008-05-08
Self-healing chip-to-chip interface Grant 7,362,697 - Becker , et al. April 22, 2	2008-04-22
Self-healing Chip-to-chip Interface App 20080074998 - BECKER; WIREN DALE ; et al.	2008-03-27
Adjustable switchpoint receiver Grant 7,202,723 - Dreps , et al. April 10, 2	2007-04-10
Data processing system and method with dynamic idle for tunable interface calibration Grant 7,117,126 - Floyd , et al. October 3, 2	2006-10-03
Digitally tunable high-current current reference with high PSRR App 20060181337 - Dreps; Daniel Mark ; et al.	2006-08-17
Adjustable switchpoint receiver App 20060076995 - Dreps; Daniel Mark ; et al.	2006-04-13
Method and apparatus for interface signaling using single-ended and differential data signals Grant 6,933,752 - Dreps , et al. August 23, 2	2005-08-23
Comparator and method for detecting a signal using a reference derived from a differential data signal pair Grant 6,922,085 - Dreps , et al. July 26, 2	2005-07-26
Modable dynamic terminator for high speed digital communications Grant 6,906,550 - Dreps , et al. June 14, 2	2005-06-14
Method and apparatus for supplying a reference voltage for chip-to-chip communication Grant 6,891,406 - Dreps , et al. May 10, 2	2005-05-10
Modable dynamic terminator for high speed digital communications App 20040246021 - Dreps, Daniel Mark ; et al.	2004-12-09
Boundary scannable one bit precompensated CMOS driver with compensating pulse width control Grant 6,772,250 - Dreps , et al. August 3, 2	2004-08-03
Method and apparatus for supplying a reference voltage for chip-to-chip communication App 20040139261 - Dreps, Daniel Mark ; et al.	2004-07-15
Self-healing chip-to-chip interface App 20040136319 - Becker, Wiren Dale ; et al.	2004-07-15
Phase detector Grant 6,762,626 - Dreps , et al. July 13, 2	2004-07-13
Method and apparatus for testing, characterizing and tuning a chip interface Grant 6,735,543 - Douskey , et al. May 11, 2	2004-05-11
Apparatus for connecting circuit modules Grant 6,725,304 - Arimilli , et al. April 20, 2	2004-04-20
Comparator and method for detecting a signal using a reference derived from a differential data signal pair App 20040051565 - Dreps, Daniel Mark ; et al.	2004-03-18
Selectable interface for interfacing integrated circuit modules Grant 6,703,866 - Arimilli , et al. March 9, 2	2004-03-09
Elastic interface apparatus and method therefor Grant 6,671,753 - Dreps , et al. December 30, 2	2003-12-30
Dynamic wave-pipelined interface apparatus and methods therefor Grant 6,654,897 - Dreps , et al. November 25, 2	2003-11-25
Dynamically producing an effective impedance of an output driver with a bounded variation during transitions thereby reducing jitter Grant 6,600,347 - Borkenhagen , et al. July 29, 2	2003-07-29
Method and apparatus for testing, characterizing and tuning a chip interface App 20030101015 - Douskey, Steven Michael ; et al.	2003-05-29
Elastic interface for master-slave communication Grant 6,571,346 - Dreps , et al. May 27, 2	2003-05-27
Cascaded differential receiver circuit Grant 6,549,971 - Cecchi , et al. April 15, 2	2003-04-15
Dynamically Producing An Effective Impedance Of An Output Driver With A Bounded Variation During Transitions Thereby Reducing Jitter App 20030067327 - Borkenhagen, John Michael ; et al.	2003-04-10
System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock Grant 6,542,999 - Dreps , et al. April 1, 2	2003-04-01
Data processing system and method with dynamic idle for tunable interface calibration App 20030046596 - Floyd, Michael Stephen ; et al.	2003-03-06
Dynamic duty cycle adjuster Grant 6,501,313 - Boerstler , et al. December 31, 2	2002-12-31
Method and apparatus for inteface signaling using single-ended and differential data signals App 20020180480 - Dreps, Daniel Mark ; et al.	2002-12-05
Pseudo-differential parallel source synchronous bus App 20020152340 - Dreps, Daniel Mark ; et al.	2002-10-17
Boundary scannable one bit precompensated cmos driver with compensating pulse width control App 20020133650 - Dreps, Daniel Mark ; et al.	2002-09-19
Method and system for data transfer Grant 6,442,223 - Dreps , et al. August 27, 2	2002-08-27
Dynamic duty cycle adjuster App 20020079940 - Boerstler, David William ; et al.	2002-06-27
Apparatus for connecting circuit modules App 20020078280 - Arimilli, Ravi Kumar ; et al.	2002-06-20
Elastic interface apparatus and method therefor App 20020013875 - Dreps, Daniel Mark ; et al.	2002-01-31
Smart memory interface Grant 6,292,903 - Coteus , et al. September 18, 2	2001-09-18
Dynamic line termination clamping circuit Grant 6,127,840 - Coteus , et al. October 3, 2	2000-10-03
Sinusoidal clock signal distribution using resonant transmission lines Grant 6,098,176 - Coteus , et al. August 1, 2	2000-08-01
Variable voltage, variable impedance CMOS off-chip driver and receiver interface and circuits Grant 6,060,905 - Bickford , et al. May 9, 2	2000-05-09
Method and apparatus for coupled phase locked loops Grant 5,949,262 - Dreps , et al. September 7, 1	1999-09-07
CMOS high-speed differential to single-ended converter circuit Grant 5,821,809 - Boerstler , et al. October 13, 1	1998-10-13

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