Dour; Navneet

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dour; Navneet.The latest application filed is for "duty cycle correction system and low dropout (ldo) regulator based delay-locked loop (dll)".

Company Profile

4.15.16

Dour; Navneet - El Dorado Hills CA
Dour; Navneet - Folsom CA
Dour; Navneet - Fair Oaks CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Duty Cycle Correction System And Low Dropout (ldo) Regulator Based Delay-locked Loop (dll) App 20210320652 - Martin; Aaron ; et al.	2021-10-14
Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) Grant 11,070,200 - Martin , et al. July 20, 2	2021-07-20
Dynamically programmable memory test traffic router Grant 11,042,315 - Pappu , et al. June 22, 2	2021-06-22
Platform debug and testing with secured hardware Grant 10,613,955 - Pappu , et al.	2020-04-07
Duty Cycle Correction System And Low Dropout (ldo) Regulator Based Delay-locked Loop (dll) App 20200106430 - Martin; Aaron ; et al.	2020-04-02
Dynamically Programmable Memory Test Traffic Router App 20190042131 - PAPPU; Lakshminarayana ; et al.	2019-02-07
Platform Debug And Testing With Secured Hardware App 20190042382 - PAPPU; Lakshminarayana ; et al.	2019-02-07
Extended synchronized clock Grant 7,751,274 - Dour , et al. July 6, 2	2010-07-06
Wake-up circuit Grant 7,746,135 - Schneider , et al. June 29, 2	2010-06-29
Calibrating integrating receivers for source synchronous protocol Grant 7,602,859 - Cheng , et al. October 13, 2	2009-10-13
Wake-up Circuit App 20090085618 - Schneider; Jacob S. ; et al.	2009-04-02
Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations Grant 7,432,731 - Bains , et al. October 7, 2	2008-10-07
PVT controller for programmable on die termination Grant 7,403,034 - Dour , et al. July 22, 2	2008-07-22
Extended synchronized clock App 20080065922 - Dour; Navneet ; et al.	2008-03-13
Method and apparatus for optimizing strobe to clock relationship Grant 7,307,900 - Salmon , et al. December 11, 2	2007-12-11
Method to calibrate DRAM Ron and ODT values over PVT App 20070007992 - Bains; Kuljit S. ; et al.	2007-01-11
Integrating receivers for source synchronous protocol App 20060245473 - Cheng; Roger K. ; et al.	2006-11-02
Calibrating integrating receivers for source synchronous protocol App 20060245519 - Cheng; Roger K. ; et al.	2006-11-02
Method and apparatus for optimizing strobe to clock relationship App 20060114742 - Salmon; Joe ; et al.	2006-06-01
Method and apparatus for PVT controller for programmable on die termination Grant 7,020,818 - Dour , et al. March 28, 2	2006-03-28
Slew rate at buffers by isolating predriver from driver Grant 7,012,451 - Srikanth , et al. March 14, 2	2006-03-14
Dynamically activated memory controller data termination Grant 7,009,894 - Mukker , et al. March 7, 2	2006-03-07
Signal drive de-emphasis for memory bus App 20060002482 - Walker; Clinton ; et al.	2006-01-05
Method and apparatus for PVT controller for programmable on die termination App 20050194991 - Dour, Navneet ; et al.	2005-09-08
Dynamically Activated Memory Controller Data Termination App 20050185480 - Mukker, Anoop ; et al.	2005-08-25
Slew rate at buffers by isolating predriver from driver App 20050013071 - Srikanth, Adhiveeraraghavan ; et al.	2005-01-20
Slew rate at buffers by isolating predriver from driver Grant 6,617,891 - Srikanth , et al. September 9, 2	2003-09-09
Driver impedance control mechanism Grant 6,563,337 - Dour May 13, 2	2003-05-13
Slew rate at buffers by isolating predriver from driver App 20030058006 - Srikanth, Adhiveeraraghavan ; et al.	2003-03-27
Driver impedance control mechanism App 20030001611 - Dour, Navneet	2003-01-02
Circuit for independent power-up sequencing of a multi-voltage chip Grant 6,236,250 - Salmon , et al. May 22, 2	2001-05-22

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