Douglass; Stephen M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Douglass; Stephen M..The latest application filed is for "method and apparatus for processing data within a programmable gate array using fixed and programmable processors".

Company Profile

0.20.3

Douglass; Stephen M. - Saratoga CA
Douglass; Stephen M. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor Grant 7,539,848 - Douglass , et al. May 26, 2	2009-05-26
Programmable gate array and embedded circuitry initialization and processing Grant 7,420,392 - Schultz , et al. September 2, 2	2008-09-02
Testing of an integrated circuit having an embedded processor Grant 7,406,670 - Ansari , et al. July 29, 2	2008-07-29
Testing of an integrated circuit having an embedded processor Grant 7,269,805 - Ansari , et al. September 11, 2	2007-09-11
Speed verification of an embedded processor in a programmable logic device Grant 7,231,621 - Herron , et al. June 12, 2	2007-06-12
Method and apparatus for processing data with a programmable gate array using fixed and programmable processors Grant 7,194,600 - Douglass , et al. March 20, 2	2007-03-20
Method of designing integrated circuit having both configurable and fixed logic circuitry Grant 6,961,919 - Douglass November 1, 2	2005-11-01
Method and apparatus for processing data within a programmable gate array using fixed and programmable processors App 20050149695 - Douglass, Stephen M. ; et al.	2005-07-07
Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion Grant 6,886,092 - Douglass , et al. April 26, 2	2005-04-26
Programmable gate array and embedded circuitry initialization and processing App 20050040850 - Schultz, David P. ; et al.	2005-02-24
Programmable gate array having interconnecting logic to support embedded fixed logic circuitry Grant 6,798,239 - Douglass , et al. September 28, 2	2004-09-28
Floor planning for programmable gate array having embedded fixed logic circuitry Grant 6,693,452 - Ansari , et al. February 17, 2	2004-02-17
User configurable memory system having local and global memory blocks Grant 6,662,285 - Douglass , et al. December 9, 2	2003-12-09
Programmable gate array having interconnecting logic to support embedded fixed logic circuitry App 20030062922 - Douglass, Stephen M. ; et al.	2003-04-03
User configurable on-chip memory system Grant 6,522,167 - Ansari , et al. February 18, 2	2003-02-18
High speed configuration independent programmable macrocell Grant RE37,577 - Liu , et al. March 12, 2	2002-03-12
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Grant 6,243,664 - Nazarian , et al. June 5, 2	2001-06-05
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability Grant 5,689,686 - Nazarian , et al. November 18, 1	1997-11-18
High speed configuration independent programmable macrocell Grant 5,621,338 - Liu , et al. April 15, 1	1997-04-15
High speed configuration independent programmable macrocell Grant 5,502,403 - Liu , et al. March 26, 1	1996-03-26
OR array architecture for a programmable logic device Grant 5,467,029 - Taffe , et al. November 14, 1	1995-11-14
Architecture of high speed synchronous state machine Grant 5,023,484 - Pathak , et al. * June 11, 1	1991-06-11
Dual I/O macrocell for high speed synchronous state machine Grant 4,879,481 - Pathak , et al. November 7, 1	1989-11-07

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