Patent | Date |
---|
Semiconductor structures with deep trench capacitor and methods of manufacture Grant 10,707,217 - Donaton , et al. | 2020-07-07 |
Semiconductor Structures With Deep Trench Capacitor And Methods Of Manufacture App 20180337185 - DONATON; Ricardo A. ;   et al. | 2018-11-22 |
Semiconductor structures with deep trench capacitor and methods of manufacture Grant 10,037,998 - Donaton , et al. July 31, 2 | 2018-07-31 |
Semiconductor Structures With Deep Trench Capacitor And Methods Of Manufacture App 20170213835 - DONATON; Ricardo A. ;   et al. | 2017-07-27 |
Semiconductor structures with deep trench capacitor and methods of manufacture Grant 9,679,917 - Donaton , et al. June 13, 2 | 2017-06-13 |
DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods Grant 9,653,535 - Breil , et al. May 16, 2 | 2017-05-16 |
DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods Grant 9,496,329 - Breil , et al. November 15, 2 | 2016-11-15 |
Semiconductor Structures With Deep Trench Capacitor And Methods Of Manufacture App 20160181253 - DONATON; Ricardo A. ;   et al. | 2016-06-23 |
Semiconductor Structures With Deep Trench Capacitor And Methods Of Manufacture App 20160181249 - BRIEND; Guillaume D. ;   et al. | 2016-06-23 |
DT capacitor with silicide outer electrode and/or compressive stress layer, and related methods Grant 9,299,766 - Breil , et al. March 29, 2 | 2016-03-29 |
Dt Capacitor With Silicide Outer Electrode And/or Compressive Stress Layer, And Related Methods App 20150357403 - Breil; Nicolas L. ;   et al. | 2015-12-10 |
Dt Capacitor With Silicide Outer Electrode And/or Compressive Stress Layer, And Related Methods App 20150357402 - Breil; Nicolas L. ;   et al. | 2015-12-10 |
Dt Capacitor With Silicide Outer Electrode And/or Compressive Stress Layer, And Related Methods App 20150279925 - Breil; Nicolas L. ;   et al. | 2015-10-01 |
Hybrid bonding interface for 3-dimensional chip integration Grant 8,349,729 - Barth , et al. January 8, 2 | 2013-01-08 |
Method and structure for gate height scaling with high-k/metal gate technology Grant 8,227,870 - Chudzik , et al. July 24, 2 | 2012-07-24 |
Method for removing threshold voltage adjusting layer with external acid diffusion process Grant 8,227,307 - Chen , et al. July 24, 2 | 2012-07-24 |
Hybrid Bonding Interface For 3-dimensional Chip Integration App 20120171818 - Barth; Karl W. ;   et al. | 2012-07-05 |
Method And Structure For Gate Height Scaling With High-k/metal Gate Technology App 20120126335 - CHUDZIK; Michael P. ;   et al. | 2012-05-24 |
Hybrid bonding interface for 3-dimensional chip integration Grant 8,159,060 - Barth , et al. April 17, 2 | 2012-04-17 |
Method and structure for gate height scaling with high-k/metal gate technology Grant 8,138,037 - Chudzik , et al. March 20, 2 | 2012-03-20 |
Hybrid Bonding Interface For 3-dimensional Chip Integration App 20110101537 - Barth; Karl W. ;   et al. | 2011-05-05 |
CMOS structure including differential channel stressing layer compositions Grant 7,875,511 - Yaocheng , et al. January 25, 2 | 2011-01-25 |
Direct contact between high-.kappa./metal gate and wiring process flow Grant 7,863,123 - Bu , et al. January 4, 2 | 2011-01-04 |
Method For Removing Threshold Voltage Adjusting Layer With External Acid Diffusion Process App 20100330810 - Chen; Kuang-Jung ;   et al. | 2010-12-30 |
Method And Structure For Gate Height Scaling With High-k/metal Gate Technology App 20100237435 - Chudzik; Michael P. ;   et al. | 2010-09-23 |
High performance stress-enhance MOSFET and method of manufacture Grant 7,791,144 - Chidambarrao , et al. September 7, 2 | 2010-09-07 |
Direct Contact Between High-k/metal Gate And Wiring Process Flow App 20100181630 - Bu; Huiming ;   et al. | 2010-07-22 |
Semiconductor structure for low parasitic gate capacitance Grant 7,709,910 - Henson , et al. May 4, 2 | 2010-05-04 |
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20100013024 - Chidambarrao; Dureseti ;   et al. | 2010-01-21 |
High performance stress-enhance MOSFET and method of manufacture Grant 7,615,418 - Chidambarrao , et al. November 10, 2 | 2009-11-10 |
High performance stress-enhance MOSFET and method of manufacture Grant 7,608,489 - Chidambarrao , et al. October 27, 2 | 2009-10-27 |
Silicon/silcion germaninum/silicon body device with embedded carbon dopant Grant 7,560,326 - Mocuta , et al. July 14, 2 | 2009-07-14 |
Nitrogen based plasma process for metal gate MOS device Grant 7,498,271 - Donaton , et al. March 3, 2 | 2009-03-03 |
Semiconductor Structure For Low Parasitic Gate Capacitance App 20080258234 - Henson; William K. ;   et al. | 2008-10-23 |
Cmos Structure Including Differential Channel Stressing Layer Compositions App 20080224218 - Liu; Yaocheng ;   et al. | 2008-09-18 |
Silicon/silcion Germaninum/silicon Body Device With Embedded Carbon Dopant App 20070257249 - Mocuta; Anda C. ;   et al. | 2007-11-08 |
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20070254423 - Chidambarrao; Dureseti ;   et al. | 2007-11-01 |
High Performance Stress-enhance Mosfet And Method Of Manufacture App 20070254422 - Chidambarrao; Dureseti ;   et al. | 2007-11-01 |
Anisotropic etching of organic-containing insulating layers Grant 6,844,266 - Maex , et al. January 18, 2 | 2005-01-18 |
Anisotropic etching of organic-containing insulating layers App 20030162407 - Maex, Karen ;   et al. | 2003-08-28 |
Anisotropic etching of organic-containing insulating layers App 20020076935 - Maex, Karen ;   et al. | 2002-06-20 |