Dokumaci; Omer H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Dokumaci; Omer H..The latest application filed is for "high performance stress-enhanced mosfets using si:c and sige epitaxial source/drain and method of manufacture".

Company Profile

0.88.94

Dokumaci; Omer H. - Gainesville FL
Dokumaci; Omer H. - Istanbul TR
Dokumaci; Omer H. - Wappingers Falls NY
Dokumaci; Omer H. - Hartsdale NY
Dokumaci; Omer H - Wappingers Falls NY
Dokumaci, Omer H. - Wappinger Falls NY
Dokumaci, Omer H. - Wapplngers Falls NY
Dokumaci; Omer H. - Wappingers Fall NY
Dokumaci; Omer H. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 9,401,424 - Chen , et al. July 26, 2	2016-07-26
Silicon device on SI:C-OI and SGOI and method of manufacture Grant 9,040,373 - Chidambarrao , et al. May 26, 2	2015-05-26
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 9,023,698 - Chen , et al. May 5, 2	2015-05-05
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 8,901,566 - Chen , et al. December 2, 2	2014-12-02
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20140322873 - Chen; Huajie ; et al.	2014-10-30
Silicon Device On Si:c-oi And Sgoi And Method Of Manufacture App 20140103366 - CHIDAMBARRAO; Dureseti ; et al.	2014-04-17
Silicon device on Si: C-oi and Sgoi and method of manufacture Grant 8,633,071 - Chidambarrao , et al. January 21, 2	2014-01-21
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20120196412 - CHEN; Huajie ; et al.	2012-08-02
Silicon device on Si:C-OI and SGOI and method of manufacture Grant 8,232,153 - Chidambarrao , et al. July 31, 2	2012-07-31
High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 8,168,489 - Chen , et al. May 1, 2	2012-05-01
Silicon Device On Si: C-oi And Sgoi And Method Of Manufacture App 20120052653 - CHIDAMBARRAO; Duresetl ; et al.	2012-03-01
Silicon device on Si:C SOI and SiGe and method of manufacture Grant 8,119,472 - Chidambarrao , et al. February 21, 2	2012-02-21
Ultra shallow junction formation by epitaxial interface limited diffusion Grant 8,067,805 - Chen , et al. November 29, 2	2011-11-29
Embedded stressed nitride liners for CMOS performance improvement Grant 8,013,397 - Chidambarrao , et al. September 6, 2	2011-09-06
FinFETs single-sided implant formation Grant 7,994,612 - Anderson , et al. August 9, 2	2011-08-09
Strained silicon on relaxed sige film with uniform misfit dislocation density Grant 7,964,865 - Chidambarrao , et al. June 21, 2	2011-06-21
Self-aligned planar double-gate transistor structure Grant 7,960,790 - Dokumaci , et al. June 14, 2	2011-06-14
Anti-halo compensation Grant 7,952,149 - Dokumaci , et al. May 31, 2	2011-05-31
Halo-first ultra-thin SOI FET for superior short channel control Grant 7,859,061 - Dokumaci , et al. December 28, 2	2010-12-28
Ultra shallow junction formation by epitaxial interface limited diffusion Grant 7,816,237 - Chen , et al. October 19, 2	2010-10-19
Anti-halo compensation Grant 7,754,569 - Dokumaci , et al. July 13, 2	2010-07-13
Structure and method to improve channel mobility by gate electrode stress modification Grant 7,750,410 - Belyansky , et al. July 6, 2	2010-07-06
MOSFET performance improvement using deformation in SOI structure Grant 7,745,277 - Chidambarrao , et al. June 29, 2	2010-06-29
Method for fabricating a semiconductor structure Grant 7,732,288 - Zhu , et al. June 8, 2	2010-06-08
Sidewall semiconductor transistors Grant 7,696,025 - Zhu , et al. April 13, 2	2010-04-13
Transistor having high mobility channel and methods Grant 7,682,887 - Dokumaci , et al. March 23, 2	2010-03-23
Halo-first Ultra-thin Soi Fet For Superior Short Channel Control App 20090294854 - Dokumaci; Omer H. ; et al.	2009-12-03
Embedded stressed nitride liners for CMOS performance improvement Grant 7,615,454 - Chidambarrao , et al. November 10, 2	2009-11-10
FINFETs SINGLE-SIDED IMPLANT FORMATION App 20090261425 - Anderson; Brent A. ; et al.	2009-10-22
Halo-first ultra-thin SOI FET for superior short channel control Grant 7,595,247 - Dokumaci , et al. September 29, 2	2009-09-29
Strained Si on multiple materials for bulk or SOI substrates Grant 7,560,328 - Chidambarrao , et al. July 14, 2	2009-07-14
Method For Fabricating A Semiconductor Structure App 20090142894 - Zhu; Huilong ; et al.	2009-06-04
Strained dislocation-free channels for CMOS and method of manufacture Grant 7,495,291 - Chidambarrao , et al. February 24, 2	2009-02-24
Backgated FinFET having different oxide thicknesses Grant 7,476,946 - Bryant , et al. January 13, 2	2009-01-13
Methods to improve the SiGe heterojunction bipolar device performance Grant 7,476,914 - Dokumaci , et al. January 13, 2	2009-01-13
Halo-first Ultra-thin Soi Fet For Superior Short Channel Control App 20080290409 - Dokumaci; Omer H. ; et al.	2008-11-27
Sidewall Semiconductor Transistors App 20080286909 - Zhu; Huilong ; et al.	2008-11-20
Self-aligned planar double-gate transistor structure Grant 7,453,123 - Dokumaci , et al. November 18, 2	2008-11-18
Self-aligned Planar Double-gate Transistor Structure App 20080246090 - Dokumaci; Omer H. ; et al.	2008-10-09
Ultra Shallow Junction Formation By Epitaxial Interface Limited Diffusion App 20080230840 - Chen; Huajie ; et al.	2008-09-25
Ultra Shallow Junction Formation By Epitaxial Interface Limited Diffusion App 20080233687 - Chen; Huajie ; et al.	2008-09-25
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,410,846 - Chidambarrao , et al. August 12, 2	2008-08-12
Ultra shallow junction formation by epitaxial interface limited diffusion Grant 7,402,870 - Chen , et al. July 22, 2	2008-07-22
Embedded Stressed Nitride Liners For Cmos Performance Improvement App 20080164532 - Chidambarrao; Dureseti ; et al.	2008-07-10
Sidewall semiconductor transistors Grant 7,397,081 - Zhu , et al. July 8, 2	2008-07-08
METHODS TO IMPROVE THE SiGe HETEROJUNCTION BIPOLAR DEVICE PERFORMANCE App 20080128861 - Dokumaci; Omer H. ; et al.	2008-06-05
Stress inducing spacers Grant 7,374,987 - Chidambarrao , et al. May 20, 2	2008-05-20
Embedded stressed nitride liners for CMOS performance improvement Grant 7,361,973 - Chidambarrao , et al. April 22, 2	2008-04-22
Anti-halo Compensation App 20080070391 - Dokumaci; Omer H. ; et al.	2008-03-20
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,345,329 - Chidambarrao , et al. March 18, 2	2008-03-18
Embedded Stressed Nitride Liners For Cmos Performance Improvement App 20080044974 - Chidambarrao; Dureseti ; et al.	2008-02-21
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20070296038 - CHEN; Huajie ; et al.	2007-12-27
Dual stressed SOI substrates Grant 7,312,134 - Chidambarrao , et al. December 25, 2	2007-12-25
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture Grant 7,303,949 - Chen , et al. December 4, 2	2007-12-04
Method for reduced N+ diffusion in strained Si on SiGe substrate Grant 7,297,601 - Chidambarrao , et al. November 20, 2	2007-11-20
High Performance Stress-enhanced Mosfets Using Si:c And Sige Epitaxial Source/drain And Method Of Manufacture App 20070264783 - CHEN; Huajie ; et al.	2007-11-15
Silicon Device On Si: C-oi And Sgoi And Method Of Manufacture App 20070228472 - Chidambarrao; Dureseti ; et al.	2007-10-04
Silicon Device On Si: C-oi And Sgoi And Method Of Manufacture App 20070231979 - CHIDAMBARRAO; Dureseti ; et al.	2007-10-04
Ultra-thin channel device with raised source and drain and solid source extension doping Grant 7,271,446 - Dokumaci , et al. September 18, 2	2007-09-18
Dual Stressed Soi Substrates App 20070202639 - Chidambarrao; Dureseti ; et al.	2007-08-30
Dual stressed SOI substrates Grant 7,262,087 - Chidambarrao , et al. August 28, 2	2007-08-28
Mosfet Wth High Angle Sidewall Gate And Contacts For Reduced Miller Capacitance App 20070184621 - Chidambarrao; Dureseti ; et al.	2007-08-09
Silicon device on Si:C-OI and SGOI and method of manufacture Grant 7,247,534 - Chidambarrao , et al. July 24, 2	2007-07-24
STRAINED Si ON MULTIPLE MATERIALS FOR BULK OR SOI SUBSTRATES App 20070166897 - Chidambarrao; Dureseti ; et al.	2007-07-19
Self-aligned Planar Double-gate Process By Self-aligned Oxidation App 20070138556 - Dokumaci; Omer H. ; et al.	2007-06-21
Strained Si on multiple materials for bulk or SOI substrates Grant 7,223,994 - Chidambarrao , et al. May 29, 2	2007-05-29
MOSFET with high angle sidewall gate and contacts for reduced miller capacitance Grant 7,224,021 - Chidambarrao , et al. May 29, 2	2007-05-29
Transistor Having High Mobility Channel And Methods App 20070087540 - Dokumaci; Omer H. ; et al.	2007-04-19
Self-aligned planar double-gate process by self-aligned oxidation Grant 7,205,185 - Dokumaci , et al. April 17, 2	2007-04-17
Strained finFETs and method of manufacture Grant 7,198,995 - Chidambarrao , et al. April 3, 2	2007-04-03
Multiple Low And High K Gate Oxides On Single Gate For Lower Miller Capacitance And Improved Drive Current App 20070063277 - Belyansky; Michael P. ; et al.	2007-03-22
Mosfet With High Angle Sidewall Gate And Contacts For Reduced Miller Capacitance App 20070057334 - Chidambarrao; Dureseti ; et al.	2007-03-15
Backgated FinFET having different oxide thicknesses Grant 7,187,042 - Bryant , et al. March 6, 2	2007-03-06
High performance FET with laterally thin extension Grant 7,176,116 - Cabral, Jr. , et al. February 13, 2	2007-02-13
NFETs using gate induced stress modulation Grant 7,144,767 - Chidambarrao , et al. December 5, 2	2006-12-05
Methods to improve the SiGe heterojunction bipolar device performance Grant 7,144,787 - Dokumaci , et al. December 5, 2	2006-12-05
Anti-halo Compensation App 20060255375 - Dokumaci; Omer H. ; et al.	2006-11-16
Methods To Improve The Sige Heterojunction Bipolar Device Performance App 20060252216 - Dokumaci; Omer H. ; et al.	2006-11-09
Backgated Finfet Having Different Oxide Thicknesses App 20060237774 - BRYANT; Andres ; et al.	2006-10-26
Method and structure for improved MOSFETs using poly/silicide gate height control Grant 7,091,563 - Chidambarrao , et al. August 15, 2	2006-08-15
Transistor Having High Mobility Channel And Methods App 20060166417 - Dokumaci; Omer H. ; et al.	2006-07-27
Increasing Doping Of Well Compensating Dopant Region According To Increasing Gate Length App 20060154428 - Dokumaci; Omer H.	2006-07-13
Backgated Finfet Having Different Oxide Thicknesses App 20060145195 - Bryant; Andres ; et al.	2006-07-06
NFETs using gate induced stress modulation App 20060145274 - Chidambarrao; Dureseti ; et al.	2006-07-06
Dual Stressed Soi Substrates App 20060125008 - Chidambarrao; Dureseti ; et al.	2006-06-15
Sidewall Semiconductor Transistors App 20060124993 - Zhu; Huilong ; et al.	2006-06-15
Nanocircuit and self-correcting etching method for fabricating same App 20060118825 - Dokumaci; Omer H. ; et al.	2006-06-08
Backgated FinFET having different oxide thicknesses Grant 7,056,773 - Bryant , et al. June 6, 2	2006-06-06
Lowered Source/Drain Transistors App 20060108651 - Zhu; Huilong ; et al.	2006-05-25
Method of manufacturing a disposable reversed spacer process for high performance recessed channel CMOS Grant 7,041,538 - Ieong , et al. May 9, 2	2006-05-09
Method of manufacturing strained dislocation-free channels for CMOS Grant 7,037,770 - Chidambarrao , et al. May 2, 2	2006-05-02
Apparatus and method for staircase raised source/drain structure Grant 7,037,818 - Dokumaci , et al. May 2, 2	2006-05-02
Ultra Shallow Junction Formation By Epitaxial Interface Limited Diffusion App 20060076627 - Chen; Huajie ; et al.	2006-04-13
Nanocircuit and self-correcting etching method for fabricating same Grant 7,026,247 - Dokumaci , et al. April 11, 2	2006-04-11
Method for reduced N+ diffusion in strained Si on SiGe substrate App 20060073649 - Chidambarrao; Dureseti ; et al.	2006-04-06
Apparatus And Method For Staircase Raised Source/drain Structure App 20060040484 - Dokumaci; Omer H. ; et al.	2006-02-23
Structure and method to improve channel mobility by gate electrode stress modification App 20050282325 - Belyansky, Michael P. ; et al.	2005-12-22
Isolation structures for imposing stress patterns App 20050280051 - Chidambarrao, Dureseti ; et al.	2005-12-22
Structure and method to improve channel mobility by gate electrode stress modification Grant 6,977,194 - Belyansky , et al. December 20, 2	2005-12-20
Structure and method to preserve STI during etching App 20050275060 - Dokumaci, Omer H. ; et al.	2005-12-15
Isolation structures for imposing stress patterns Grant 6,974,981 - Chidambarrao , et al. December 13, 2	2005-12-13
Strained Si on multiple materials for bulk or SOI substrates App 20050269561 - Chidambarrao, Dureseti ; et al.	2005-12-08
Embedded stressed nitride liners for CMOS performance improvement App 20050258515 - Chidambarrao, Dureseti ; et al.	2005-11-24
Structure and method to improve channel mobility by gate electrode stress modification App 20050245017 - Belyansky, Michael P. ; et al.	2005-11-03
Backgated Finfet Having Diferent Oxide Thicknesses App 20050245009 - Bryant, Andres ; et al.	2005-11-03
High performance FET with laterally thin extension Grant 6,933,577 - Cabral, Jr. , et al. August 23, 2	2005-08-23
Strained silicon on relaxed sige film with uniform misfit dislocation density App 20050164477 - Chidambarrao, Dureseti ; et al.	2005-07-28
CMOS performance enhancement using localized voids and extended defects App 20050148134 - Dokumaci, Omer H. ; et al.	2005-07-07
High performance FET with laterally thin extension App 20050148142 - Cabral, Cyril JR. ; et al.	2005-07-07
Method for reduced N+ diffusion in strained Si on SiGe substrate App 20050145992 - Chidambarrao, Dureseti ; et al.	2005-07-07
Method and structure for improved MOSFETs using poly/silicide gate height control App 20050145950 - Chidambarrao, Dureseti ; et al.	2005-07-07
MOSFET performance improvement using deformation in SOI structure App 20050142788 - Chidambarrao, Dureseti ; et al.	2005-06-30
Strained dislocation-free channels for CMOS and method of manufacture App 20050139930 - Chidambarrao, Dureseti ; et al.	2005-06-30
Strained finFETs and method of manufacture App 20050130358 - Chidambarrao, Dureseti ; et al.	2005-06-16
Silicon device on Si:C-OI and SGOI and method of manufacture App 20050104131 - Chidambarrao, Dureseti ; et al.	2005-05-19
Method and structure for improved MOSFETs using poly/silicide gate height control Grant 6,890,808 - Chidambarrao , et al. May 10, 2	2005-05-10
Structure and method to improve channel mobility by gate electrode stress modification App 20050093059 - Belyansky, Michael P. ; et al.	2005-05-05
MOSFET performance improvement using deformation in SOI structure Grant 6,887,751 - Chidambarrao , et al. May 3, 2	2005-05-03
Nanocircuit and self-correcting etching method for fabricating same App 20050087809 - Dokumaci, Omer H. ; et al.	2005-04-28
High Performance Fet With Laterally Thin Extension App 20050087824 - Cabral, Cyril JR. ; et al.	2005-04-28
Strained dislocation-free channels for CMOS and method of manufacture App 20050085022 - Chidambarrao, Dureseti ; et al.	2005-04-21
High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture App 20050082616 - Chen, Huajie ; et al.	2005-04-21
Low-GIDL MOSFET structure and method for fabrication Grant 6,878,582 - Dokumaci , et al. April 12, 2	2005-04-12
CMOS performance enhancement using localized voids and extended defects Grant 6,878,978 - Dokumaci , et al. April 12, 2	2005-04-12
High performance logic and high density embedded dram with borderless contact and antispacer Grant 6,873,010 - Chidambarrao , et al. March 29, 2	2005-03-29
Strained silicon on relaxed sige film with uniform misfit dislocation density Grant 6,872,641 - Chidambarrao , et al. March 29, 2	2005-03-29
NFETs using gate induced stress modulation App 20050064646 - Chidambarrao, Dureseti ; et al.	2005-03-24
Strained Silicon On Relaxed Sige Film With Uniform Misfit Dislocation Density App 20050064686 - Chidambarrao, Dureseti ; et al.	2005-03-24
Silicide Proximity Structures For Cmos Device Performance Improvements App 20050064687 - Chidambarrao, Dureseti ; et al.	2005-03-24
Silicide proximity structures for CMOS device performance improvements Grant 6,869,866 - Chidambarrao , et al. March 22, 2	2005-03-22
Self-aligned planar double-gate process by self-aligned oxidation App 20050059252 - Dokumaci, Omer H. ; et al.	2005-03-17
METHOD AND STRUCTURE FOR IMPROVED MOSFETs USING POLY/SILICIDE GATE HEIGHT CONTROL App 20050054148 - Chidambarrao, Dureseti ; et al.	2005-03-10
Method For Reduced N+ Diffusion In Strained Si On Sige Substrate App 20050054145 - Chidambarrao, Dureseti ; et al.	2005-03-10
Stress inducing spacers App 20050040460 - Chidambarrao, Dureseti ; et al.	2005-02-24
CMOS performance enhancement using localized voids and extended defects Grant 6,858,488 - Dokumaci , et al. February 22, 2	2005-02-22
Ultra-thin channel device with raised source and drain and solid source extension doping App 20050014314 - Dokumaci, Omer H. ; et al.	2005-01-20
Low-GIDL MOSFET structure and method for fabrication Grant 6,841,826 - Dokumaci , et al. January 11, 2	2005-01-11
Cmos Performance Enhancement Using Localized Voids And Extended Defects App 20050003605 - Dokumaci, Omer H. ; et al.	2005-01-06
CMOS performance enhancement using localized voids and extended defects App 20050003604 - Dokumaci, Omer H. ; et al.	2005-01-06
Self-aligned planar double-gate process by amorphization Grant 6,833,569 - Dokumaci , et al. December 21, 2	2004-12-21
Low-GIDL MOSFET structure and method for fabrication App 20040248356 - Dokumaci, Omer H. ; et al.	2004-12-09
Stress inducing spacers Grant 6,825,529 - Chidambarrao , et al. November 30, 2	2004-11-30
Ultra-thin channel device with raised source and drain and solid source extension doping Grant 6,812,105 - Dokumaci , et al. November 2, 2	2004-11-02
Damascene method for improved MOS transistor Grant 6,806,534 - Dokumaci , et al. October 19, 2	2004-10-19
Method for blocking implants from the gate of an electronic device via planarizing films Grant 6,803,315 - Dokumaci , et al. October 12, 2	2004-10-12
Amorphous and polycrystalline silicon nanolaminate App 20040171177 - Dokumaci, Omer H. ; et al.	2004-09-02
Cmos Performance Enhancement Using Localized Voids And Extended Defects App 20040166624 - Dokumaci, Omer H. ; et al.	2004-08-26
MOS transistor Grant 6,780,694 - Doris , et al. August 24, 2	2004-08-24
Amorphous and polycrystalline silicon nanolaminate Grant 6,764,883 - Dokumaci , et al. July 20, 2	2004-07-20
Low-GIDL MOSFET structure and method for fabrication App 20040137689 - Dokumaci, Omer H. ; et al.	2004-07-15
Damascene Method For Improved Mos Transistor App 20040135212 - Dokumaci, Omer H. ; et al.	2004-07-15
Amorphous And Polycrystalline Silicon Nanolaminate App 20040129941 - Dokumaci, Omer H. ; et al.	2004-07-08
Mos Transistor App 20040132236 - Doris, Bruce B. ; et al.	2004-07-08
Self-aligned planar double-gate process by amorphization App 20040121549 - Dokumaci, Omer H. ; et al.	2004-06-24
Stress inducing spacers App 20040113217 - Chidambarrao, Dureseti ; et al.	2004-06-17
Isolation structures for imposing stress patterns App 20040113174 - Chidambarrao, Dureseti ; et al.	2004-06-17
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS App 20040104433 - Ieong, Meikei ; et al.	2004-06-03
High performance logic and high density embedded dram with borderless contact and antispacer App 20040075111 - Chidambarrao, Dureseti ; et al.	2004-04-22
High performance logic and high density embedded dram with borderless contact and antispacer Grant 6,709,926 - Chidambarrao , et al. March 23, 2	2004-03-23
Method for blocking implants from the gate of an electronic device via planarizing films App 20040023500 - Dokumaci, Omer H. ; et al.	2004-02-05
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS Grant 6,677,646 - Ieong , et al. January 13, 2	2004-01-13
Method for differential oxidation rate reduction for n-type and p-type materials Grant 6,667,197 - Gluschenkov , et al. December 23, 2	2003-12-23
High Performance Logic And High Density Embedded Dram With Borderless Contact And Antispacer App 20030224573 - Chidambarrao, Dureseti ; et al.	2003-12-04
Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation Grant 6,657,244 - Dokumaci , et al. December 2, 2	2003-12-02
Structure and method to preserve STI during etching Grant 6,645,867 - Dokumaci , et al. November 11, 2	2003-11-11
Method of making thermally stable planarizing films Grant 6,642,147 - Dokumaci , et al. November 4, 2	2003-11-04
Structure and method to preserve STI during etching App 20030199166 - Dokumaci, Omer H. ; et al.	2003-10-23
Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS App 20030189228 - Ieong, Meikei ; et al.	2003-10-09
Anti-spacer structure for improved gate activation App 20030162388 - Dokumaci, Omer H. ; et al.	2003-08-28
Anti-spacer structure for improved gate activation Grant 6,586,289 - Dokumaci , et al. July 1, 2	2003-07-01
Method of improving gate activation by employing atomic oxygen enhanced oxidation Grant 6,566,210 - Ajmera , et al. May 20, 2	2003-05-20
Method of protecting semiconductor areas while exposing a gate Grant 6,562,713 - Belyansky , et al. May 13, 2	2003-05-13
Anti-spacer structure for self-aligned independent gate implantation Grant 6,531,365 - Dokumaci , et al. March 11, 2	2003-03-11
Method of making thermally stable planarizing films App 20030038109 - Dokumaci, Omer H. ; et al.	2003-02-27
Method Of Improving Gate Activation By Employing Atomic Oxygen Enhanced Oxidation App 20030010972 - Ajmera, Atul C. ; et al.	2003-01-16
Anti-spacer Structure For Self-aligned Independent Gate Implantation App 20020197839 - Dokumaci, Omer H. ; et al.	2002-12-26
Structure and method to preserve STI during etching App 20020175146 - Dokumaci, Omer H. ; et al.	2002-11-28
Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer Grant 6,329,704 - Akatsu , et al. December 11, 2	2001-12-11
Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer App 20010030333 - Akatsu, Hiroyuki ; et al.	2001-10-18

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