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Loop Buffering Employing Loop Characteristic Prediction In A Processor For Optimizing Loop Buffer Performance
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Instruction swap for patching problematic instructions in a microprocessor
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Instruction Swap For Patching Problematic Instructions In A Microprocessor
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Structure for supporting simultaneous storage of trace and standard cache lines
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Tracking effective addresses in an out-of-order processor
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Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
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Apparatus And Method For Using Branch Prediction Heuristics For Determination Of Trace Formation Readiness
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Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
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Detecting and Handling Short Forward Branch Conversion Candidates
App 20100262813 - Brown; Mary D. ; et al. | 2010-10-14 |
Tracking Effective Addresses in an Out-of-Order Processor
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Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches
Grant 7,779,232 - Doing , et al. August 17, 2 | 2010-08-17 |
Apparatus and method for decreasing the latency between instruction cache and a pipeline processor
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Data processing system, processor and method of data processing having improved branch target address cache
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Apparatus and method for supporting simultaneous storage of trace and standard cache lines
Grant 7,644,233 - Davis , et al. January 5, 2 | 2010-01-05 |
Apparatus and method for saving power in a trace cache
Grant 7,610,449 - Davis , et al. October 27, 2 | 2009-10-27 |
Method for providing zero overhead looping using carry chain masking
Grant 7,558,948 - Bybell , et al. July 7, 2 | 2009-07-07 |
Method and Apparatus for Dynamically Managing Instruction Buffer Depths for Non-Predicted Branches
App 20090063819 - Doing; Richard W. ; et al. | 2009-03-05 |
Structure For Supporting Simultaneous Storage Of Trace And Standard Cache Lines
App 20080250205 - DAVIS; GORDON T. ; et al. | 2008-10-09 |
Structure For Using Branch Prediction Heuristics For Determination Of Trace Formation Readiness
App 20080250206 - Davis; Gordon T. ; et al. | 2008-10-09 |
Design Structure For Cache Maintenance
App 20080250207 - DAVIS; GORDON T. ; et al. | 2008-10-09 |
Structure For Instruction Cache Trace Formation
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Structure For Register Renaming In A Microprocessor
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Apparatus And Method For Decreasing The Latency Between Instruction Cache And A Pipeline Processor
App 20080177981 - Dieffenderfer; James N. ; et al. | 2008-07-24 |
Instruction Cache Trace Formation
App 20080120468 - Davis; Gordon T. ; et al. | 2008-05-22 |
Data Processing System, Processor and Method of Data Processing Having Improved Branch Target Address Cache
App 20080120496 - Bradford; Jeffrey P. ; et al. | 2008-05-22 |
Apparatus and Method for Cache Maintenance
App 20080114964 - Davis; Gordon T. ; et al. | 2008-05-15 |
Apparatus and Method for Saving Power in a Trace Cache
App 20080086595 - Davis; Gordon T. ; et al. | 2008-04-10 |
Apparatus and Method for Supporting Simultaneous Storage of Trace and Standard Cache Lines
App 20080086596 - Davis; Gordon T. ; et al. | 2008-04-10 |
Apparatus and Method for Using Branch Prediction Heuristics for Determination of Trace Formation Readiness
App 20080086597 - Davis; Gordon T. ; et al. | 2008-04-10 |
Method and Apparatus for Register Renaming in a Microprocessor
App 20080077778 - Davis; Gordon T. ; et al. | 2008-03-27 |
Method for software controllable dynamically lockable cache line replacement system
Grant 7,321,954 - Dieffenderfer , et al. January 22, 2 | 2008-01-22 |
Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
Grant 7,281,120 - Dieffenderfer , et al. October 9, 2 | 2007-10-09 |
Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor
App 20060155961 - Dieffenderfer; James N. ; et al. | 2006-07-13 |
Method and system for providing zero overhead looping using carry chain masking
App 20060095751 - Bybell; Anthony J. ; et al. | 2006-05-04 |
Method for software controllable dynamically lockable cache line replacement system
App 20060036811 - Dieffenderfer; James N. ; et al. | 2006-02-16 |
Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor
App 20050216703 - Dieffenderfer, James N. ; et al. | 2005-09-29 |
Thread switch tuning tool for optimal performance in a computer processor
Grant 6,018,759 - Doing , et al. January 25, 2 | 2000-01-25 |
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